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74F823SPC

Part # 74F823SPC
Description IC D-TYPE POS TRG SNGL 24DIP
Category IC
Availability In Stock
Qty 7
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Fairchild Semiconductor
Date Code: 8822
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

© 1999 Fairchild Semiconductor Corporation DS009596 www.fairchildsemi.com
April 1988
Revised August 1999
74F823 9-Bit D-Type Flip-Flop
74F823
9-Bit D-Type Flip-Flop
General Description
The 74F823 is a 9-bit buffered register. It features Clock
Enable and Clear which are ideal for parity bus interfacing
in high performance microprogramming systems.
Features
3-STATE outputs
Clock Enable and Clear
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number Package Number Package Description
74F823SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F823SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
www.fairchildsemi.com 2
74F823
Unit Loading/Fan Out
Functional Description
The 74F823 device consists of nine D-type edge-triggered
flip-flops. It has 3-STATE true outputs and is organized in
broadside pinning. The buffered Clock (CP) and buffered
Output Enable (OE
) are common to all flip-flops. The flip-
flops will store the state of their individual D inputs that
meet the setup and hold times requirements on the LOW-
to-HIGH CP transition. With the OE
LOW the contents of
the flip-flops are available at the outputs. When the OE
is
HIGH, the outputs go to the high impedance state. Opera-
tion of the OE
input does not affect the state of the flip-
flops. In addition to the Clock and Output Enable pins, the
74F823 has Clear (CLR
) and Clock Enable (EN) pins.
When the CLR
is LOW and the OE is LOW, the outputs are
LOW. When CLR
is HIGH, data can be entered into the flip-
flops. When EN
is LOW, data on the inputs is transferred to
the outputs on the LOW-to-HIGH clock transition. When
the EN
is HIGH, the outputs do not change state regard-
less of the data or clock inputs transitions. This device is
ideal for parity bus interfacing in high performance sys-
tems.
Function Table
L = LOW Voltage Level
H = HIGH Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
NC = No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names Description
U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
D
0
–D
8
Data Inputs 1.0/1.0 20 µA/0.6 mA
OE
Output Enable Input 1.0/1.0 20 µA/0.6 mA
CLR
Clear 1.0/1.0 20 µA/0.6 mA
CP Clock Input 1.0/2.0 20 µA/1.2 mA
EN
Clock Enable 1.0/1.0 20 µA/0.6 mA
O
0
–O
8
3-STATE Outputs 150/40 (33.3) 3 mA/24 mA (20 mA)
Inputs Internal Output
Function
OE
CLR EN CP D Q O
HHLHXNC Z Hold
HHLLXNC Z Hold
H H H X X NC Z Hold
LHHXXNC NCHold
H L X X X H Z Clear
L L X X X H L Clear
HHL
H H Z Load
HHL
H L Z Load
LHL
L H L Data Available
LHL
H L H Data Available
L H L H X NC NC No Change in Data
L H L L X NC NC No Change in Data
3 www.fairchildsemi.com
74F823
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature 65°C to +150°C
Ambient Temperature under Bias 55°C to +125°C
Junction Temperature under Bias 55°C to +150°C
V
CC
Pin Potential to Ground Pin 0.5V to +7.0V
Input Voltage (Note 2) 0.5V to +7.0V
Input Current (Note 2) 30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
= 0V)
Standard Output 0.5V to V
CC
3-STATE Output 0.5V to +5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
(mA)
Free Air Ambient Temperature 0°C to +70°C
Supply Voltage +4.5V to +5.5V
Symbol Parameter Min Typ Max Units
V
CC
Conditions
V
IH
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage 1.2 V Min I
IN
= 18 mA
V
OH
Output HIGH 10% V
CC
2.5
VMin
I
OH
= 1 mA
Voltage 10% V
CC
2.4 I
OH
= 3 mA
5% V
CC
2.7 I
OH
= 1 mA
5% V
CC
2.7 I
OH
= 3 mA
V
OL
Output LOW
10% V
CC
0.5 V Min I
OL
= 24 mA
Voltage
I
IH
Input HIGH
5.0 µAMaxV
IN
= 2.7V
Current
I
BVI
Input HIGH Current
7.0 µAMaxV
IN
= 7.0V
Breakdown Test
I
CEX
Output HIGH
50 µAMaxV
OUT
= V
CC
Leakage Current
V
ID
Input Leakage
4.75 V 0.0
I
ID
= 1.9 µA
Test All Other Pins Grounded
I
OD
Output Leakage
3.75 µA0.0
V
IOD
= 150 mV
Circuit Current All Other Pins Grounded
I
IL
Input LOW 0.6 mA Max
V
IN
= 0.5V (OE, CLR, EN)
Current 1.2 mA Max V
IN
= 0.5V (CP)
I
OZH
Output Leakage Current 50 µAMaxV
OUT
= 2.7V
I
OZL
Output Leakage Current 50 µAMaxV
OUT
= 0.5V
I
OS
Output Short-Circuit Current 60 150 mA Max V
OUT
= 0V
I
ZZ
Buss Drainage Test 500 µA0.0VV
OUT
= 5.25V
I
CCZ
Power Supply Current 75 100 mA Max V
O
= HIGH Z
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