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74F675APC

Part # 74F675APC
Description IC REG SER-IN SER-PAR OUT 24-DIP
Category IC
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National Semiconductor Corp
Date Code: 9512
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

© 1999 Fairchild Semiconductor Corporation DS009587 www.fairchildsemi.com
April 1988
Revised August 1999
74F675A 16-Bit Serial-In, Serial/Parallel-Out Shift Register
74F675A
16-Bit Serial-In, Serial/Parallel-Out Shift Register
General Description
The 74F675A contains a 16-bit serial in/serial out shift reg-
ister and a 16-bit parallel out storage register. Separate
serial input and output pins are provided for expansion to
longer words. By means of a separate clock, the contents
of the shift register are transferred to the storage register.
The contents of the storage register can also be loaded
back into the shift register. A HIGH signal on the Chip
Select input prevents both shifting and parallel loading.
Features
Serial-to-parallel converter
16-Bit serial I/O shift register
16-Bit parallel out storage register
Recirculating parallel transfer
Expandable for longer words
Slim 24 lead package
74F675A version prevents false clocking through
CS
or R/W inputs
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number Package Number Package Description
74F675ASC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F675APC N24A 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide
74F675ASPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
www.fairchildsemi.com 2
74F675A
Unit Loading/Fan Out
Functional Description
The 16-Bit shift register operates in one of four modes, as
determined by the signals applied to the Chip Select (CS
),
Read/Write (R/W
) and Store Clock Pulse (STCP) input.
State changes are indicated by the falling edge of the Shift
Clock Pulse (SHCP
). In the Shift Right mode, data enters
D
0
from the Serial Input (SI) pin and exits from Q
15
via the
Serial Data Output (SO) pin. In the Parallel Load mode,
data from the storage register outputs enter the shift regis-
ter and serial shifting is inhibited.
The storage register is in the Hold mode when either CS
or
R/W
is HIGH. With CS and R/W both LOW, the storage
register is parallel loaded from the shift register on the ris-
ing edge of STCP.
To prevent false clocking of the shift register, SHCP
should
be in the LOW state during a LOW-to-HIGH transition of
CS
. To prevent false clocking of the storage register, STCP
should be LOW during a HIGH-to-LOW transition of CS
if
R/W
is LOW, and should also be LOW during a HIGH-to-
LOW transition of R/W
if CS is LOW.
Shift Register Operations Table Storage Register Operations Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= HIGH-to-LOW Transition
= LOW-to-HIGH Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names Description
U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
SI Serial Data Input 1.0/1.0 20 µA/0.6 mA
CS
Chip Select Input (Active LOW) 1.0/1.0 20 µA/0.6 mA
SHCP
Shift Clock Pulse Input (Active Falling Edge) 1.0/1.0 20 µA/0.6 mA
STCP Store Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/0.6 mA
R/W
Read/Write Input 1.0/1.0 20 µA/0.6 mA
SO Serial Data Output 50/33.3 1 mA/20 mA
Q
0
–Q
15
Parallel Data Outputs 50/33.3 1 mA/20 mA
Control Inputs Operating
CS
R/W SHCP STCP Mode
H X X X Hold
LL
X Shift Right
LH
L Shift Right
LH
H Parallel Load,
No Shifting
Inputs Operating
CS
R/W STCP Mode
HXXHold
LHXHold
LL
Parallel Load
3 www.fairchildsemi.com
74F675A
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature 65°C to +150°C
Ambient Temperature under Bias 55°C to +125°C
Junction Temperature under Bias 55°C to +150°C
V
CC
Pin Potential to Ground Pin 0.5V to +7.0V
Input Voltage (Note 2) 0.5V to +7.0V
Input Current (Note 2) 30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
= 0V)
Standard Output 0.5V to V
CC
3-STATE Output 0.5V to +5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
(mA)
Free Air Ambient Temperature 0°C to +70°C
Supply Voltage +4.5V to +5.5V
Symbol Parameter Min Typ Max Units
V
CC
Conditions
V
IH
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage 1.2 V Min I
IN
= 18 mA
V
OH
Output HIGH 10% V
CC
2.5
VMin
I
OH
= 1 mA
Voltage 5% V
CC
2.7 I
OH
= 1 mA
V
OL
Output LOW
10% V
CC
0.5 V Min I
OL
= 20 mA
Voltage
I
IH
Input HIGH
5.0 µAMaxV
IN
= 2.7V
Current
I
BVI
Input HIGH Current
7.0 µAMaxV
IN
= 7.0V
Breakdown Test
I
CEX
Output HIGH
50 µAMaxV
OUT
= V
CC
Leakage Current
V
ID
Input Leakage
4.75 V 0.0
I
ID
= 1.9 µA
Tes t All Other Pins Grounded
I
OD
Output Leakage
3.75 µA0.0
V
IOD
= 150 mV
Circuit Current All Other Pins Grounded
I
IL
Input LOW Current 0.6 mA Max V
IN
= 0.5V
I
OS
Output Short-Circuit Current 60 150 mA Max V
OUT
= 0V
I
CCH
Power Supply Current 106 160 mA Max V
O
= HIGH
I
CCL
Power Supply Current 106 160 mA Max V
O
= LOW
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