Philips Semiconductors Product specification
74F5381-of-8 decoder (3-State)
2
1989 Apr 06 853–1273 96267
DESCRIPTION
The 74F538 decoder/demultiplexer accepts three address (A0 - A2)
input signals and decodes them to select one of eight mutually
exclusive outputs. A Polarity control (P) input determines whether
the outputs are active Low or active High. The 74F538 has 3-State
outputs, and a High signal on the Output Enables (OE
n) inputs will
force all outputs to the high impedance state. Two active High (E2,
E3) and two active Low (E
0, E1) inputs are available for easy
expansion to 1-of-32 decoding with four packages, or for data
demultiplexing to 1-of-8 or 1-of-16 destinations.
TYPE
TYPICAL
PROPAGATION DELAY
TYPICAL SUPPLY
CURRENT
(TOTAL)
74F538 8.5ns 35mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V ±10%,
T
amb
= 0°C to +70°C
PKG DWG #
20-Pin Plastic DIP N74F538N SOT146-1
20-Pin Plastic SOL N74F538D SOT163-1
PIN CONFIGURATION
20
19
18
17
16
15
14
13
12
10 11
9
8
7
6
5
4
3
2
1
V
CC
Q3
Q4
A2
E2
E3
P
Q7
Q2
Q1
Q0
A0
A1
Q5
Q6
GND
E
0
E1
OE1
OE
0
SF00996
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION
74F(U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
A0 - A2 Address inputs 1.0/1.0 20µA/0.6mA
E0, E1 Enable inputs (active Low) 1.0/1.0 20µA/0.6mA
E2, E3 Enable inputs (active High) 1.0/1.0 20µA/0.6mA
P Polarity control input 1.0/1.0 20µA/0.6mA
OE0, OE1 Output Enable inputs 1.0/1.0 20µA/0.6mA
Q0 - Q7 Data outputs 150/40 3.0mA/24mA
NOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
6717
V
CC
= Pin 20
GND = Pin 10
32119188911
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
P
E0
E1
E2
E3
OE0
OE1
12
16
15
14
13
4
5
A0 A1 A2
SF00997
LOGIC SYMBOL (IEEE/IEC)
6
7
17
13
19
DMUX
1
2
3
5
0,8
0
2
G
0
7
SF00998
11
9
8
18
1,8
2,8
3,8
4,8
5,8
6,8
7,8
14
15
16
4
&
&
N8
EN
