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74AC521MTC

Part # 74AC521MTC
Description IC COMPARATOR IDENTITY 20TSSOP
Category IC
Availability In Stock
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Fairchild Semiconductor
Date Code: 0521
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

© 2005 Fairchild Semiconductor Corporation DS009964 www.fairchildsemi.com
November 1988
Revised March 2005
74AC521 • 74ACT521 8-Bit Identity Comparator
74AC521 74ACT521
8-Bit Identity Comparator
General Description
The AC/ACT521 is an expandable 8-bit comparator. It com-
pares two words of up to eight bits each and provides a
LOW output when the two words match bit for bit. The
expansion input I
A B
also serves as an active LOW enable
input.
Features
I
CC
reduced by 50%
Compares two 8-bit words in 6.5 ns typ
Expandable to any word length
20-pin package
Outputs source/sink 24 mA
ACT521 has TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering table.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
FACT is a trademark of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74AC521SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74AC521SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC521MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC521PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74ACT521SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74ACT521SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT521MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT521PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Pin Names Description
A
0
A
7
Word A Inputs
B
0
B
7
Word B Inputs
T
A B
Expansion or Enable Input
O
A B
Identity Output
www.fairchildsemi.com 2
74AC521 74ACT521
Truth Table
H HIGH Voltage Level
L
LOW Voltage Level
Note 1: A
0
B
0
, A
1
B
1
, A
2
B
2
, etc.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Applications
Ripple Expansion
Parallel Expansion
Inputs Outputs
I
A B
A, B
O
A B
L A B (Note 1) L
L A
H
H A
B (Note 1) H
H A
H
3 www.fairchildsemi.com
74AC521 74ACT521
Absolute Maximum Ratings(Note 2) Recommended Operating
Conditions
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, output/input loading variables. Fairchild does not rec-
ommend operation of FACT
circuits outside databook specifications.
DC Electrical Characteristics for AC
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: I
IN
and I
CC
@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V
CC
.
Supply Voltage (V
CC
) 0.5V to 7.0V
DC Input Diode Current (I
IK
)
V
I
0.5V 20 mA
V
I
V
CC
0.5V 20 mA
DC Input Voltage (V
I
) 0.5V to V
CC
0.5V
DC Output Diode Current (I
OK
)
V
O
0.5V 20 mA
V
O
V
CC
0.5V 20 mA
DC Output Voltage (V
O
) 0.5V to V
CC
0.5V
DC Output Source
or Sink Current (I
O
) 50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
) 50 mA
Storage Temperature (T
STG
) 65 C to 150 C
Junction Temperature (T
J
)
PDIP 140
C
Supply Voltage (V
CC
)
AC 2.0V to 6.0V
ACT 4.5V to 5.5V
Input Voltage (V
I
) 0V to V
CC
Output Voltage (V
O
) 0V to V
CC
Operating Temperature (T
A
) 40 C to 85 C
Minimum Input Edge Rate (
V/ t)
AC Devices
V
IN
from 30% to 70% of V
CC
V
CC
@ 3.3V, 4.5V, 5.5V 125 mV/ns
Minimum Input Edge Rate (
V/ t)
ACT Devices
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V 125 mV/ns
Symbol Parameter
V
CC
T
A
25 CT
A
40 C to 85 C
Units Conditions
(V) Typ Guaranteed Limits
V
IH
Minimum HIGH Level 3.0 1.5 2.1 2.1 V
OUT
0.1V
Input Voltage 4.5 2.25 3.15 3.15 V or V
CC
0.1V
5.5 2.75 3.85 3.85
V
IL
Maximum LOW Level 3.0 1.5 0.9 0.9 V
OUT
0.1V
Input Voltage 4.5 2.25 1.35 1.35 V or V
CC
0.1V
5.5 2.75 1.65 1.65
V
OH
Minimum HIGH Level 3.0 2.99 2.9 2.9
Output Voltage 4.5 4.49 4.4 4.4 V I
OUT
50 A
5.5 5.49 5.4 5.4
V
IN
V
IL
or V
IH
3.0 2.56 2.46 I
OH
= 12 mA
4.5 3.86 3.76 V I
OH
= 24 mA
5.5 4.86 4.76 I
OH
= 24 mA (Note 3)
V
OL
Maximum LOW Level 3.0 0.002 0.1 0.1
Output Voltage 4.5 0.001 0.1 0.1 V I
OUT
50 A
5.5 0.001 0.1 0.1
V
IN
V
IL
or V
IH
3.0 0.36 0.44 I
OL
= 12 mA
4.5 0.36 0.44 V I
OL
= 24 mA
5.5 0.36 0.44 I
OL
= 24 mA (Note 3)
I
IN
Maximum Input
5.5 0.1 1.0 AV
I
V
CC
, GND
(Note 5) Leakage Current
I
OLD
Minimum Dynamic 5.5 75 mA V
OLD
1.65V Max
I
OHD
Output Current (Note 4) 5.5 75 mA V
OHD
3.85V Min
I
CC
Maximum Quiescent
5.5 4.0 40.0 A
V
IN
V
CC
(Note 5) Supply Current or GND
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