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74ABT16374BDL

Part # 74ABT16374BDL
Description
Category IC
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Technical Document


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Philips Semiconductors Product specification
74ABT16374B
74ABTH16374B
16-bit D-type flip-flop; positive-edge trigger
(3-State)
1998 Feb 27
4
FUNCTION TABLE
INPUTS
INTERNAL
OUTPUTS
OPERATING MODE
nOE nCP nDx
REGISTER
nQ0 – nQ7
OPERATING
MODE
L
L
l
h
L
H
L
H
Load and read register
L X NC NC Hold
H
H
X
nDx
NC
nDx
Z
Z
Disable outputs
H = High voltage level
h = High voltage level one set-up time prior to the High-to-Low E transition
L = Low voltage level
l = Low voltage level one set-up time prior to the High-to-Low E transition
NC= No change
X = Don’t care
Z = High impedance “off” state
= Low-to-High clock transition
= Not a Low-to-High clock transition
ABSOLUTE MAXIMUM RATINGS
1,
2
SYMBOL
PARAMETER CONDITIONS RATING UNIT
V
CC
DC supply voltage –0.5 to +7.0 V
I
IK
DC input diode current V
I
< 0 –18 mA
V
I
DC input voltage
3
–1.2 to +7.0 V
I
OK
DC output diode current V
O
< 0 –50 mA
V
OUT
DC output voltage
3
output in Off or High state –0.5 to +5.5 V
I
O
DC out
p
ut current
output in Low state 128
mA
I
OUT
DC
o
u
tp
u
t
c
u
rrent
output in High state –64
mA
T
stg
Storage temperature range –65 to 150 °C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN MAX
UNIT
V
CC
DC supply voltage 4.5 5.5 V
V
I
Input voltage 0 V
CC
V
V
IH
High-level input voltage 2.0 V
V
IL
Low-level Input voltage 0.8 V
I
OH
High-level output current –32 mA
I
OL
Low-level output current 64 mA
t/v Input transition rise or fall rate 0 10 ns/V
T
amb
Operating free-air temperature range –40 +85 °C
Philips Semiconductors Product specification
74ABT16374B
74ABTH16374B
16-bit D-type flip-flop; positive-edge trigger
(3-State)
1998 Feb 27
5
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL PARAMETER TEST CONDITIONS T
amb
= +25°C
T
amb
= –40°C
to +85°C
UNIT
MIN TYP MAX MIN MAX
V
IK
Input clamp voltage V
CC
= 4.5V; I
IK
= –18mA –0.9 –1.2 –1.2 V
V
CC
= 4.5V; I
OH
= –3mA; V
I
= V
IL
or V
IH
2.5 2.9 2.5
V
OH
High-level output voltage V
CC
= 5.0V; I
OH
= –3mA; V
I
= V
IL
or V
IH
3.0 3.4 3.0
V
V
CC
= 4.5V; I
OH
= –32mA; V
I
= V
IL
or V
IH
2.0 2.4 2.0
V
OL
Low-level output voltage V
CC
= 4.5V; I
OL
= 64mA; V
I
= V
IL
or V
IH
0.42 0.55 0.55 V
V
RST
Power-up output voltage
3
V
CC
= 5.5V; I
O
= 1mA; V
I
= GND or V
CC
0.13 0.55 0.55 V
Input leakage current
I
I
npu
t
l
ea
k
a
g
e curren
t
V
CC
=55V
;
V =V
CC
or GND
001
±1
±1
µA
I
I
g
74ABT16374B
V
CC
=
5
.
5V
;
V
I
=
V
CC
or
GND
0
.
01
±1
±1
µ
A
I
74ABT16374B
CC I CC
µ
In
p
ut leakage current
V
CC
= 5.5V; V
I
= V
CC
or
GND
Control pins ±0.01 ±1 ±1
I
I
In ut
leakage
current
74ABTH16374B V
CC
= 5.5V; V
I
= V
CC
p
0.01 1 1
µA
V
CC
= 5.5V; V
I
= 0
–1 –3 –5
B H ld t i t
6
V
CC
= 4.5V; V
I
= 0.8V 50 50
I
HOLD
Bus Hold current inputs
6
74ABTH16374B
V
CC
= 4.5V; V
I
= 2.0V –75 –75
µA
74ABTH16374B
V
CC
= 5.5V; V
I
= 0 to 5.5V ±800
I
OFF
Power-off leakage current V
CC
= 0.0V; V
O
or V
I
4.5V ±5.0 ±100 ±100 µA
I
PU/PD
Power-up/down 3-State
output current
4
V
CC
= 2.1V; V
O
= 0.5V;
V
I
= GND or V
CC
; V
OE
= GND
±5.0 ±50 ±50 µA
I
OZH
3-State output High current V
CC
= 5.5V; V
O
= 2.7V; V
I
= V
IL
or V
IH
0.5 10 10 µA
I
OZL
3-State output Low current V
CC
= 5.5V; V
O
= 0.5V; V
I
= V
IL
or V
IH
–0.5 –10 –10 µA
I
CEX
Output High leakage current V
CC
= 5.5V; V
O
= 5.5V; V
I
= GND or V
CC
5.0 50 50 µA
I
O
Output current
1
V
CC
= 5.5V; V
O
= 2.5V –50 –70 –180 –50 –180 mA
I
CCH
V
CC
= 5.5V; Outputs High, V
I
= GND or V
CC
0.5 2 2 mA
I
CCL
Quiescent supply current V
CC
= 5.5V; Outputs Low, V
I
= GND or V
CC
8 19 19 mA
I
CCZ
V
CC
= 5.5V; Outputs 3-State;
V
I
= GND or V
CC
0.5 2 2 mA
I
CC
Additional supply current
per input pin
2
74ABT16374B
V
CC
= 5.5V; one input at 3.4V, other inputs at
V
CC
or GND
5 100 100 µA
I
CC
Additional supply current
per input pin
2
74ABTH16374B
V
CC
= 5.5V; one input at 3.4V, other inputs at
V
CC
or GND
0.5 1.5 1.5 mA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V
CC
between 0V and 2.1V with a transition time of up to 10msec. From V
CC
= 2.1V to V
CC
= 5V ± 10% a
transition time of up to 100µsec is permitted.
5. Unused pins at V
CC
or GND.
6. This is the bus hold overdrive current required to force the input to the opposite logic state.
Philips Semiconductors Product specification
74ABT16374B
74ABTH16374B
16-bit D-type flip-flop; positive-edge trigger
(3-State)
1998 Feb 27
6
AC CHARACTERISTICS
GND = 0V, t
R
= t
F
= 2.5ns, C
L
= 50pF, R
L
= 500
LIMITS
SYMBOL PARAMETER WAVEFORM
T
amb
= +25°C
V
CC
= +5.0V
T
amb
= –40 to +85°C
V
CC
= +5.0V ±0.5V
UNIT
MIN TYP MAX MIN MAX
f
MAX
Maximum clock frequency 1 180 260 MHz
t
PLH
t
PHL
Propagation delay
nCP to nQx
1
1.7
1.4
2.6
2.2
4.0
3.4
1.7
1.4
4.7
3.9
ns
t
PZH
t
PZL
Output enable time
to High and Low level
3
4
1.3
1.3
2.4
2.3
3.7
3.4
1.3
1.3
4.7
4.6
ns
t
PHZ
t
PLZ
Output disable time
from High and Low level
3
4
1.9
1.7
3.1
2.6
4.6
4.0
1.9
1.7
5.5
4.4
ns
AC SETUP REQUIREMENTS
GND = 0V, t
R
= t
F
= 2.5ns, C
L
= 50pF, R
L
= 500
LIMITS
SYMBOL PARAMETER WAVEFORM
T
amb
= +25°C
V
CC
= +5.0V
T
amb
= –40 to +85°C
V
CC
= +5.0V ±0.5V
UNIT
MIN TYP MIN
t
s
(H)
t
s
(L)
Setup time, High or Low
nDx to nCP
2
1.0
1.0
0.3
0.1
1.0
1.0
ns
t
h
(H)
t
h
(L)
Hold time, High or Low
nDx to nCP
2
1.0
1.0
–0.1
–0.3
1.0
1.0
ns
t
w
(H)
t
w
(L)
nCP pulse width
High or Low
1
2.8
2.8
1.2
1.5
2.8
2.8
ns
AC WAVEFORMS
V
M
= 1.5V, V
IN
= GND to 3.0V
VM VM VM
VM VM
1/f
MAX
t
w
(H) t
w
(L)
t
PHL
t
PLH
nCP
nQx
SA00328
Waveform 1. Propagation Delay, Clock Input to Output, Clock
Pulse Width, and Maximum Clock Frequency
V
M
nDx
V
M
V
M
V
M
V
M
V
M
nCP
t
s
(H) t
h
(H) t
s
(L) t
h
(L)
NOTE: The shaded areas indicate when the input is permitted to
change for predictable output performance.
SA00329
Waveform 2. Data Setup and Hold Times
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