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5962R9566901VCC

Part # 5962R9566901VCC
Description
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

1
®
FN3554.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HS-2420RH
Radiation Hardened Fast Sample and Hold
The HS-2420RH is a radiation hardened monolithic circuit
consisting of a high performance operational amplifier with
its output in series with an ultra-low leakage analog switch
and MOSFET input unity gain amplifier.
With an external hold capacitor connected to the switch output,
a versatile, high performance sample-and-hold or track-and-
hold circuit is formed. When the switch is closed, the device
behaves as an operation amplifier, and any of the standard op
amp feedback networks may be connected around the device
to control gain, frequency response, etc. When the switch is
opened the output will remain at its last level.
Performance as a sample-and-hold compares very favorably
with other monolithic, hybrid, modular, and discrete circuits.
Accuracy to better than 0.01% is achievable over the
temperature range. Fast acquisition is coupled with superior
droop characteristics, even at high temperatures. High slew
rate, wide bandwidth, and low acquisition time produce
excellent dynamic characteristics. The ability to operate at
gains greater than 1 frequently eliminates the need for
external scaling amplifiers.
The device may also be used as a versatile operational
amplifier with a gated output for applications such as analog
switches, peak holding circuits, etc.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95669. A “hot-link” is provided
on our website for downloading.
Pinout
14 LEAD METAL-SEALED SIDE-BRAZED CERAMIC DIP
MIL-STD-1835, CDIP2-T14
TOP VIEW
Features
Electrically Screened to SMD # 5962-95669
QML Qualified per MIL-PRF-38535 Requirements
Maximum Acquisition Time
- 10V Step to 0.1% . . . . . . . . . . . . . . . . . . . . . . . . . . 4µs
- 10V Step to 0.01% . . . . . . . . . . . . . . . . . . . . . . . . . 6µs
Maximum Drift Current. . . . . . . . . . . . . . . . . . . . . . . 10nA
(Maximum Over Temperature)
TTL Compatible Control Input
Power Supply Rejection . . . . . . . . . . . . . . . . . . . . . 80dB
Total Dose . . . . . . . . . . . . . . . . . . . . . 100 krad(Si) (Max)
No Latch-Up
Applications
Data Acquisition Systems
D to A Deglitcher
Auto Zero Systems
Peak Detector
•Gated Op Amp
Functional Diagram
IN-
IN+
OFFSET ADJUST
OFFSET ADJUST
V-
NC
OUTPUT
SAMPLE
/HOLD
GND
NC
HOLD CAPACITOR
NC
V+
NC
CONTROL
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Ordering Information
ORDERING NUMBER
INTERNAL
MKT. NUMBER
TEMP. RANGE
(
o
C)
5962R9566901VCC HS1B-2420RH-Q -55 to 125
-
+
OFFSET
ADJUST
V+
-
+
7
OUTPUT
11
HOLD
CAPACITOR
- INPUT
+ INPUT
SAMPLE
/
HOLD
CONTROL
V-GND
14
2
1
HS-2420RH
34 5
513
Data Sheet February 2003
2
Test Circuits
FIGURE 1. TEST FIXTURE SCHEMATIC (SWITCH POSITIONS S
1
- S
8
DETERMINE CONFIGURATION)
NOTE: Compute Hold Mode Feedthrough Attenuation from the
Formula:
Where V
OUT HOLD
= Peak-Peak Value of Output Sinewave during
the Hold Mode.
FIGURE 2. HOLD MODE FEEDTHROUGH ATTENUATION
NOTE: GBWP is the Frequency of V
INPUT
at which:
FIGURE 3. GAIN BANDWIDTH PRODUCT
DUT
-
+
A
S
/H-V
CC
+V
CC
CH =
1000pF
50
2
21
1
S
2
S
1
2
1
S
6
1
2
S
7
S
7
1
2
50
V
AC
AOUT
EOUT
50
1M
4
3
2
1
S
8
3
2
S
3
1
+V
CC
GND
50pF 2k
1
S
5
OPEN 3
2S
4
1
100k
V
DC
10k
I
LOAD
NULL
AMP
X1
X-1
BUFFER
100k
ALL RESISTORS = ±1%
ALL CAPACITORS = ±10%
+
-
+
-
CH =
V
OUT
50pF2k
+15V
-15V
1000pF
DUT
V
IN
OUT
A0
ENIN2
IN1
IN3
IN4
IN5
IN6
IN7
IN8
A2
A1
SINEWAVE
INPUT
SAMPLE
/HOLD
CONTROL INPUT
+5V
+
-
FeedthroughAttenuation 20 log
V
OUT HOLD
V
IN HOLD
--------------------------------



=
CH =
V
OUT
50pF2k
+15V
-15V
1000pF
DUT
S/H
50
+
-
20 log
V
OUT
V
INPUT
---------------------



3dB=
HS-2420RH
3
FIGURE 4. ACQUISITION TIME (t
ACQ
TO 0.01% IS SHOWN, t
ACQ
TO 0.1% IS DONE IN THE SAME MANNER)
FIGURE 5.
Test Circuits (Continued)
INCREMENT t
2
BY 50ns
(50ns LONGER DELAY)
SEND SAMPLE
COMMAND
SET t
2
TO 7µs
INITIALLY
DIGITIZE V
1
AT t
1
(10µs)
DIGITIZE V
2
AT t
2
DECREMENT
t
2
BY 50ns
CALCULATE V
1
- V
2
IS V 0.01%?
NO
YES
COURSE t
ACQ
MEASUREMENT LOOP
DECREMENT
t
2
BY 50ns
DIGITIZE V
1
AT t
1
(10µs)
DIGITIZE V
2
AT t
2
CALCULATE V
1
- V
2
IS V 0.01%?
RECORD
t
ACQ
NOYES
FINE t
ACQ
MEASUREMENT LOOP
NOTE: See Test Diagram, Timing Diagram
COMPUTER
CONTROLLER
V
1
DIGITIZER
V
2
DIGITIZER
V
1
V
2
t
2
VARIABLE
DELAY
t
2
DELAY
CONTROL
t
1
10µs
1000pF
2k
t
1
-
+
-
+
S/H
CONTROL
HS-2420RH
+10V
0V
0V
-10V
OR
50pF
DELAY
HS-2420RH
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