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5962R9570801VJC

Part # 5962R9570801VJC
Description
Category IC
Availability In Stock
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Harris Corporation
Date Code: 9709
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

1
TM
File Number 3033.4
HS-6617RH
Radiation Hardened 2K x 8 CMOS PROM
The Intersil HS-6617RH is a radiation hardened 16K CMOS
PROM, organized in a 2K word by 8-bit format. The chip is
manufactured using a radiation hardened CMOS process,
and is designed to be functionally equivalent to the
HM-6617. Synchronous circuit design techniques combine
with CMOS processing to give this device high speed
performance with very low power dissipation.
On chip address latches are provided, allowing easy
interfacing with recent generation microprocessors that use
multiplexed address/data bus structure, such as the
HS-80C85RH or HS-80C86RH. The output enable control
(
G) simplifies microprocessor system interfacing by allowing
output data bus control, in addition to, the chip enable
control. Synchronous operation of the HS-6617RH is ideal
for high speed pipe-lined architecture systems and also in
synchronous logic replacement functions.
Applications for the HS-6617RH CMOS PROM include low
power microprocessor based instrumentation and
communications systems, remote data acquisition and
processing systems, processor control store, and
synchronous logic replacement.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95708. A “hot-link” is provided
on our homepage for downloading.
http://www.intersil.com/spacedefense/space.htm
Features
Electrically Screened to SMD # 5962-95708
QML Qualified per MIL-PRF-38535 Requirements
Total Dose . . . . . . . . . . . . . . . . . . . . . . 100 krad(Si) (Max)
Latch-Up Free. . . . . . . . . . . . . . . . . . . .>1 x 10
12
rad(Si)/s
Field Programmable
Functionally Equivalent to HM-6617
Pin Compatible with Intel 2716
Low Standby Power . . . . . . . . . . . . . . . . . . . 1.1mW (Max)
Low Operating Power . . . . . . . . . . . .137.5mW/MHz (Max)
Fast Access Time. . . . . . . . . . . . . . . . . . . . . .100ns (Max)
TTL Compatible Inputs/Outputs
Synchronous Operation
On Chip Address Latches
Three-State Outputs
Nicrome Fuse Links
Easy Microprocessor Interfacing
Military Temperature Range . . . . . . . . . . . -55
o
C to 125
o
C
Ordering Information
ORDERING NUMBER
INTERNAL
MKT. NUMBER
TEMP. RANGE
(
o
C)
5962R9570801QJC HS1-6617RH-8 -55 to 125
5962R9570801QXC HS9-6617RH-Q -55 to 125
5962R9570801VJC HS1-6617RH-Q -55 to 125
5962R9570801VXC HS9-6617RH-Q -55 to 125
HS1-6617RH/PROTO HS1-6617RH/PROTO -55 to 125
HS9-6617RH/PROTO HS9-6617RH/PROTO -55 to 125
Data Sheet August 2000
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
2
Pinouts
24 LEAD CERAMIC DUAL-IN-LINE
(SBDIP)
MIL-STD-1835 CDIP2-T24
TOP VIEW
24 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
(FLATPACK)
MIL-STD-1835 CDFP4-F24
TOP VIEW
Functional Diagram
1
2
3
4
5
6
7
8
9
10
11
12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
GND
16
17
18
19
20
21
22
23
24
15
14
13
VDD
A9
P
G
A10
Q7
Q5
Q4
Q3
A8
E
Q6
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
GND
VDD
A8
A9
P
G
A10
E
Q7
Q6
Q5
Q4
Q3
2
3
4
5
6
7
8
9
10
11
12
1
24
23
22
21
20
19
18
17
16
15
14
13
PIN DESCRIPTION
A Address Input
Q Data Output
E Chip Enable
G Output Enable
P Program Enable (P Hardwired to VDD, except during programming)
TRUTH TABLE
E G MODE
0 0 Enabled
0 1 Output Disabled
1 X Disabled
MSB
LSB
16
128 x 128
MATRIX
GATED
ROW
DECODER
LATCHED
ADDRESS
REGISTER
REGISTER
LATCHED ADDRESS
GATE COLUMN
DECODER
PROGRAMMING, & DATA
OUTPUT CONTROL
16 16 161616 16 16
E
E
E
8
A
4
A
4
E
8
1 OF 8
7A
7
A
128
MSB
LSB
P
E
G
A10
A9
A8
A7
A5
A4
A6
A3 A2 A1 A0
Q0 - Q7
ALL LINES POSITIVE LOGIC:
ACTIVE HIGH
THREE STATE BUFFERS:
OUTPUT ACTIVE
ADDRESS LATCHES AND GATED DECODERS:
P = HARDWIRED TO VDD EXCEPT DURING PROGRAMMING
LATCH ON FALLING EDGE OF E
GATE ON FALLING EDGE OF
G
A HIGH
HS-6617RH
3
Timing Waveform
VALID
DATA
TELQX
TGLQX
1.5V 1.5V
TGHQZ
TGLQV
1.5V1.5V
TEHQZ
1.5V
1.5V
TELEH
TEHEL
TELQV
TELAX
TAVEL
TELEL
VALID
ADDRESS
1.5V 1.5V
TAVQV
VALID
ADDRESSES
TS
3.0V
0V
0V
3.0V
0V
3.0V
ADDRESSES
DATA
OUTPUT
G
E
Q0 - Q7
FIGURE 1. READ CYCLE
Burn-In Circuits
HS-6617RH 24 LEAD SBDIP AND FLATPACK
STATIC CONFIGURATION
NOTES:
1. VDD = 6.0V ± 0.5V
2. C1 = 0.01µF (Min)
3. All Resistors = 47kΩ± 5%
4. Y = 2.7V ± 10%
HS-6617RH 24 LEAD SBDIP AND FLATPACK
DYNAMIC CONFIGURATION
NOTES:
5. VDD = 6.0V ± 0.5V
6. VIH = 4.5V± 10%
7. VIL = 0.8V (Max)
8. C1 = 0.01µF (Min)
9. All Resistors = 47kΩ± 5%
10. F0 = 100KHz ± 10%, 40 - 60% duty cycle
11. F1 = F0/2 . . . F13 = F12/2
12. Y = 2.7V ± 10%
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
GND
VDD
A8
Q3
A9
A10
Q7
Q6
Q5
Q4
E
G
P
VDD
C1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
YY
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
GND
VDD
A8
Q3
A9
A10
Q7
Q6
Q5
Q4
E
G
P
F9
C1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDD
F11
F12
VDD
F1
F13
F0
F10
F8
F7
F6
F5
F4
F3
YY
HS-6617RH
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