SIGNETICS 10175F

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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Semiconductor Components Industries, LLC, 2002
January, 2002 – Rev. 7
1 Publication Order Number:
MC10175/D
MC10175
Quint Latch
The MC10175 is a high speed, low power quint latch. It features five
D type latches with common reset and a common two–input clock.
Data is transferred on the negative edge of the clock and latched on the
positive edge. The two clock inputs are “OR”ed together.
Any change on the data input will be reflected at the outputs while
the clock is low. The outputs are latched on the positive transition of
the clock. While the clock is in the high state, a change in the
information present at the data inputs will not affect the output
information. The reset input is enabled only when the clock is in the
high state.
P
D
= 400 mW typ/pkg (No Load)
t
pd
= 2.5 ns typ (Data to Output)
t
r
, t
f
= 2.0 ns typ (20%–80%)
LOGIC DIAGRAM
V
CC1
= PIN 1
V
CC2
= PIN 16
V
EE
= PIN 8
10
14
D
C
Q
R
6
7
11
D
C
Q
R
D
C
Q
R
D
C
Q
R
D
C
Q
R
15
3
4
12
9
5
13
D0
C0
C1
RESET
D1
D3
D4
D2 2
Q0
Q1
Q3
Q4
Q2
TRUTH TABLE
D C0 C1 Reset Q
n+1
L L L X L
H L L X H
X H X L Q n
X X H L Q n
X H X H L
X X H H L
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Device Package Shipping
ORDERING INFORMATION
MC10175L CDIP–16 25 Units / Rail
MC10175P PDIP–16 25 Units / Rail
MC10175FN PLCC–20 46 Units / Rail
MARKING
DIAGRAMS
1
16
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
CDIP–16
L SUFFIX
CASE 620
MC10175L
AWLYYWW
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
10175
AWLYYWW
1
1
16
MC10175P
AWLYYWW
DIP PIN ASSIGNMENT
V
CC1
Q2
Q3
Q4
D4
C0
C1
V
EE
V
CC2
Q1
Q0
D2
D1
RESET
D0
D3
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables
on page 18 of the ON Semiconductor MECL Data Book
(DL122/D).
MC10175
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2
ELECTRICAL CHARACTERISTICS
Test Limits
Pin
Under
–30°C +25°C +85°C
Characteristic Symbol
U
n
d
er
Test
Min Max Min Typ Max Min Max
Unit
Power Supply Drain Current I
E
8 107 78 97 107 mAdc
Input Current I
inH
6
7
10
11
460
460
460
1000
290
290
290
650
290
290
290
650
µAdc
I
inL
All 0.5 0.5 0.3 µAdc
Output Voltage Logic 1 V
OH
14
15
–1.060
–1.060
–0.890
–0.890
–0.960
–0.960
–0.810
–0.810
–0.890
–0.890
–0.700
–0.700
Vdc
Output Voltage Logic 0 V
OL
14
15
–1.890
–1.890
–1.675
–1.675
–1.850
–1.850
–1.650
–1.650
–1.825
–1.825
–1.615
–1.615
Vdc
Threshold Voltage Logic 1 V
OHA
14
15
–1.080
–1.080
–0.980
–0.980
–0.910
–0.910
Vdc
Threshold Voltage Logic 0 V
OLA
14
15
–1.655
–1.655
–1.630
–1.630
–1.595
–1.595
Vdc
Switching Times (50 Load) ns
Data Input t
10+14+
t
10–14–
14
14
1.0
1.0
3.6
3.6
1.0
1.0
3.5
3.5
1.0
1.0
3.6
3.6
Clock Input t
6–14+
t
6–14–
14
14
1.0
1.0
4.7
4.7
1.0
1.0
4.3
4.3
1.0
1.0
4.4
4.4
Reset Input t
11+4–
t
11+14–
4
14
1.0
1.0
4.0
4.0
1.0
1.0
3.9
3.9
1.0
1.0
4.2
4.2
Setup TIme
Hold Time
t
setup
t
hold
14
14
2.5
1.5
2.5
1.5
2.5
1.5
Rise Time (20 to 80%) t+ 14 1.0 3.6 1.1 3.5 1.1 3.7
Fall Time (20 to 80%) t– 14 1.0 3.6 1.1 3.5 1.1 3.7
1. Individually test each input; apply V
ILmin
to pin under test.
2. Output latched to high logic state prior to test.
MC10175
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3
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@ Test Temperature V
IHmax
V
ILmin
V
IHAmin
V
ILAmax
V
EE
–30°C –0.890 –1.890 –1.205 –1.500 –5.2
+25°C –0.810 –1.850 –1.105 –1.475 –5.2
+85°C –0.700 –1.825 –1.035 –1.440 –5.2
Pin
Under
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
(V )
Characteristic Symbol
Under
Test
V
IHmax
V
ILmin
V
IHAmin
V
ILAmax
V
EE
(V
CC
)
Gnd
Power Supply Drain Current I
E
8 8 1, 16
Input Current I
inH
6
7
10
11
6
7
10
11
8
8
8
8
1, 16
1, 16
1, 16
1, 16
I
inL
All Note 1. 8 1, 16
Output Voltage Logic 1 V
OH
14
15
10
12
6
6
8
8
1, 16
1, 16
Output Voltage Logic 0 V
OL
14
15
6, 10
6, 12
8
8
1, 16
1, 16
Threshold Voltage Logic 1 V
OHA
14
15
6
6
10
12
8
8
1, 16
1, 16
Threshold Voltage Logic 0 V
OLA
14
15
6
6
10
12
8
8
1, 16
1, 16
Switching Times (50 Load) +1.11V +0.31V Pulse In Pulse Out –3.2 V +2.0 V
Data Input t
10+14+
t
10–14–
14
14
6, 7
6, 7
10
10
14
14
8
8
1, 16
1, 16
Clock Input t
6–14+
t
6–14–
14
14
7
7
10, 6
10, 6
14
14
8
8
1, 16
1, 16
Reset Input t
11+4–
t
11+14–
4
14
5
10
6
6
7, 11
7, 11
4 (2.)
14 (2.)
8
8
1, 16
1, 16
Setup TIme
Hold Time
t
setup
t
hold
14
14
7
7
6, 10
6, 10
14
14
8
8
1, 16
1, 16
Rise Time (20 to 80%) t+ 14 6, 7 10 14 8 1, 16
Fall Time (20 to 80%) t– 14 6, 7 10 14 8 1, 16
1. Individually test each input; apply V
ILmin
to pin under test.
2. Output latched to high logic state prior to test.
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
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