SIGNETICS 10174F

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SIGNETICS 8146
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

SEMICONDUCTOR TECHNICAL DATA
3–122
REV 5
Motorola, Inc. 1996
3/93
The MC10174 is a high speed dual channel multiplexer with output
enable capability. The select inputs determine one of four active data
inputs for each multiplexer. An output enable forces both outputs low
when in the high state.
P
D
= 305 mW typ/pkg (No Load)
t
pd
= 3.5 ns typ (Data to output)
t
r
, t
f
= 2.0 ns typ (20%–80%)
D00 3
D01 5
D02 4
D03 6
A 7
B9
ENABLE
14
D10 13
D11 11
D12 12
D13 10
LOGIC DIAGRAM
V
CC1
= PIN 1
V
CC2
= PIN 16
V
EE
= PIN 8
2 Q0
15 Q1
TRUTH TABLE
ENABLE ADDRESS INPUTS OUTPUTS
E B A Q0 Q1
H X X L L
L L L D00 D10
L L H D01 D11
L H L D02 D12
L H H D03 D13
DIP
PIN ASSIGNMENT
V
CC1
Q0
DO0
DO2
DO1
DO3
A
V
EE
V
CC2
Q1
ENABLE
D10
D12
D11
D13
B
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–36 of the Motorola MECL Data
Book (DL122/D).
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
MC10174
3–123 MOTOROLAMECL Data
DL122 — Rev 6
ELECTRICAL CHARACTERISTICS
Pi
Test Limits
Pin
Under
–30°C +25°C +85°C
Characteristic Symbol
Under
Test
Min Max Min Typ Max Min Max
Unit
Power Supply Drain Current I
E
8 80 58 73 80 mAdc
Input Current I
inH
4
14
350
525
220
330
220
330
µAdc
I
inL
4 0.5 0.5 0.3 µAdc
Output Voltage Logic 1 V
OH
15 –1.060 –0.890 –0.960 –0.810 –0.890 –0.700 Vdc
Output Voltage Logic 0 V
OL
15 –1.890 –1.675 –1.850 –1.650 –1.825 –1.615 Vdc
Threshold Voltage Logic 1 V
OHA
15 –1.080 –0.980 –0.910 Vdc
Threshold Voltage Logic 0 V
OLA
15 –1.655 –1.630 –1.595 Vdc
Switching Times (50 Load) ns
Propagation Delay t
13+15+
t
13–15–
t
7+15–
t
7–15+
t
14+15–
t
14–15+
15
15
15
15
15
15
1.4
1.4
1.9
1.9
1.0
1.0
5.0
5.0
6.6
6.6
3.3
3.3
1.5
1.5
2.0
2.0
1.0
1.0
3.5
3.5
5.0
5.0
2.0
2.0
4.7
4.7
6.2
6.2
3.1
3.1
1.4
1.4
2.1
2.1
0.9
0.9
5.0
5.0
6.6
6.6
3.4
3.4
Rise Time (20 to 80%) t+ 15 1.0 3.4 1.1 2.0 3.3 1.1 3.6
Fall Time (20 to 80%) t– 15 1.0 3.4 1.1 2.0 3.3 1.1 3.6
ELECTRICAL CHARACTERISTICS (continued)
Each MECL 10,000 series circuit has been designed
t t th d ifi ti h i th t t t bl
TEST VOLTAGE VALUES (Volts)
,g
to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The
circuit is in atestsocketormountedon a printed circuit
@ Test Temperature V
IHmax
V
ILmin
V
IHAmin
V
ILAmax
V
EE
circuit is in a test socket or mounted on a printed circuit
board and transverse air flow greater than 500 linear
fpm is maintained Outputs are terminated through a
–30°C –0.890 –1.890 –1.205 –1.500 –5.2
f
pm
i
s ma
i
nta
i
ne
d
.
O
utputs are term
i
nate
d
t
h
roug
h
a
50–ohm resistor to –2.0 volts. Test procedures are
shown for only one gate. The other gates are tested in
+25°C –0.810 –1.850 –1.105 –1.475 –5.2
sho
w
n
for
onl
y
one
gate
.
The
other
gates
are
tested
in
the same manner.
+85°C –0.700 –1.825 –1.035 –1.440 –5.2
Pin
Under
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
(V
CC
)
Characteristic Symbol
U
n
d
er
Test
V
IHmax
V
ILmin
V
IHAmin
V
ILAmax
V
EE
(V
CC
)
Gnd
Power Supply Drain Current I
E
8 8 1, 16
Input Current I
inH
4
14
4
14
8
8
1, 16
1, 16
I
inL
4 4 8 1, 16
Output Voltage Logic 1 V
OH
15 13 8 1, 16
Output Voltage Logic 0 V
OL
15 14 8 1, 16
Threshold Voltage Logic 1 V
OHA
15 13 8 1, 16
Threshold Voltage Logic 0 V
OLA
15 14 8 1, 16
Switching Times (50 Load) +1.11V Pulse In Pulse Out –3.2 V +2.0 V
Propagation Delay t
13+15+
t
13–15–
t
7+15–
t
7–15+
t
14+15–
t
14–15+
15
15
15
15
15
15
11
11
13
13
13
13
7
7
14
14
15
15
15
15
15
15
8
8
8
8
8
8
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
Rise Time (20 to 80%) t+ 15 13 14 15 8 1, 16
Fall Time (20 to 80%) t– 15 13 14 15 8 1, 16
MC10174
MOTOROLA MECL Data
DL122 — Rev 6
3–124
OUTLINE DIMENSIONS
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 775–02
ISSUE C
NOTES:
1. DATUMS –L–, –M–, AND –N– DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS PLASTIC
BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM –T–, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS,
GATE BURRS AND INTERLEAD FLASH, BUT
INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE
THE H DIMENSION TO BE SMALLER THAN 0.025
(0.635).
–M–
–N–
–L–
Y BRK
W
V
D
D
S
L–M
M
0.007 (0.180) N
S
T
S
L–M
M
0.007 (0.180) N
S
T
S
L–M
S
0.010 (0.250) N
S
T
X
G1
B
U
Z
VIEW D–D
20 1
S
L–M
M
0.007 (0.180) N
S
T
S
L–M
M
0.007 (0.180) N
S
T
S
L–M
S
0.010 (0.250) N
S
T
C
G
VIEW S
E
J
R
Z
A
0.004 (0.100)
–T–
SEATING
PLANE
S
L–M
M
0.007 (0.180) N
S
T
S
L–M
M
0.007 (0.180) N
S
T
H
VIEW S
K
K1
F
G1
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.385 0.395 9.78 10.03
B 0.385 0.395 9.78 10.03
C 0.165 0.180 4.20 4.57
E 0.090 0.110 2.29 2.79
F 0.013 0.019 0.33 0.48
G 0.050 BSC 1.27 BSC
H 0.026 0.032 0.66 0.81
J 0.020 ––– 0.51 –––
K 0.025 ––– 0.64 –––
R 0.350 0.356 8.89 9.04
U 0.350 0.356 8.89 9.04
V 0.042 0.048 1.07 1.21
W 0.042 0.048 1.07 1.21
X 0.042 0.056 1.07 1.42
Y ––– 0.020 ––– 0.50
Z 2 10 2 10
G1 0.310 0.330 7.88 8.38
K1 0.040 ––– 1.02 –––
12NEXT

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