SIGNETICS 10164F

Cross Number:

Item Description: Standoffs & Spacers HLSP9-06V-0 NATURAL

Qty Price
1 + $4.37000






Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Semiconductor Components Industries, LLC, 2002
January, 2002 – Rev. 7
1 Publication Order Number:
MC10164/D
MC10164
8-Line Multiplexer
The MC10164 is a high speed, low power eight–channel data
selector which routes data present at one–of–eight inputs to the output.
The data is routed according to the three bit code present on the
address inputs. An enable input is provided for easy bit expansion.
P
D
= 310 mW typ/pkg (No Load)
t
pd
= 3.0 ns typ (Data to Output)
t
r
, t
f
= 2.0 ns typ (20%–80%)
LOGIC DIAGRAM
V
CC1
= PIN 1
V
CC2
= PIN 16
V
EE
= PIN 8
A 7
B 9
C 10
Enable
2
X06
X15
X24
X33
X411
X512
X613
X714
15 Z
TRUTH TABLE
ADDRESS INPUTS
ENABLE C B A Z
L L L L X0
L L L H X1
L L H L X2
L L H H X3
L H L L X4
L H L H X5
L H H L X6
L H H H X7
H X X X L
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Device Package Shipping
ORDERING INFORMATION
MC10164L CDIP–16 25 Units / Rail
MC10164P PDIP–16 25 Units / Rail
MC10164FN PLCC–20 46 Units / Rail
MARKING
DIAGRAMS
1
16
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
CDIP–16
L SUFFIX
CASE 620
MC10164L
AWLYYWW
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
10164
AWLYYWW
1
1
16
MC10164P
AWLYYWW
DIP PIN ASSIGNMENT
V
CC2
ENABLE
X3
X2
X1
X0
A
V
EE
V
CC1
Z
X7
X6
X5
X4
C
B
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables
on page 18 of the ON Semiconductor MECL Data Book
(DL122/D).
MC10164
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2
ELECTRICAL CHARACTERISTICS
Test Limits
Pin
Under
–30°C +25°C +85°C
Characteristic Symbol
U
n
d
er
Test
Min Max Min Typ Max Min Max
Unit
Power Supply Drain Current I
E
8 83 60 75 83 mAdc
Input Current I
inH
2 425 265 265 µAdc
I
inL
4 0.5 0.5 0.3 µAdc
Output Voltage Logic 1 V
OH
15 –1.060 –0.890 –0.960 –0.810 –0.890 –0.700 Vdc
Output Voltage Logic 0 V
OL
15 –1.890 –1.675 –1.850 –1.650 –1.825 –1.615 Vdc
Threshold Voltage Logic 1 V
OHA
15 –1.080 –0.980 –0.910 Vdc
Threshold Voltage Logic 0 V
OLA
15 –1.655 –1.630 –1.595 Vdc
Switching Times (50 Load) ns
Propagation Delay t
4+15+
t
4–15–
t
7+15+
t
7–15–
t
2+15–
t
2–15+
15
15
15
15
15
15
1.5
1.5
1.9
1.9
0.9
0.9
4.9
4.9
6.5
6.5
3.5
3.5
1.5
1.5
2.0
2.0
1.0
1.0
3.0
3.0
4.0
4.0
2.0
2.0
4.7
4.7
6.2
6.2
3.1
3.1
1.6
1.6
2.2
2.2
1.0
1.0
5.0
5.0
6.7
6.7
3.3
3.3
Rise Time (20 to 80%) t+ 15 0.9 3.3 1.1 2.0 3.3 1.2 3.6
Fall Time (20 to 80%) t– 15 0.9 3.3 1.1 2.0 3.3 1.2 3.6
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@ Test Temperature V
IHmax
V
ILmin
V
IHAmin
V
ILAmax
V
EE
–30°C –0.890 –1.890 –1.205 –1.500 –5.2
+25°C –0.810 –1.850 –1.105 –1.475 –5.2
+85°C –0.700 –1.825 –1.035 –1.440 –5.2
Pin
Under
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
(V )
Characteristic Symbol
Under
Test
V
IHmax
V
ILmin
V
IHAmin
V
ILAmax
V
EE
(V
CC
)
Gnd
Power Supply Drain Current I
E
8 8 1,16
Input Current I
inH
2 4 8 1,16
I
inL
4 4 8 1,16
Output Voltage Logic 1 V
OH
15 4,9 8 1,16
Output Voltage Logic 0 V
OL
15 9 8 1,16
Threshold Voltage Logic 1 V
OHA
15 4,9 2 8 1,16
Threshold Voltage Logic 0 V
OLA
15 9 2 8 1,16
Switching Times (50 Load) +1.11V Pulse In Pulse Out –3.2 V +2.0 V
Propagation Delay t
4+15+
t
4–15–
t
7+15+
t
7–15–
t
2+15–
t
2–15+
15
15
15
15
15
15
9
9
5
5
7,5
7,5
4
4
7
7
2
2
15
15
15
15
15
15
8
8
8
8
8
8
1,16
1,16
1,16
1,16
1,16
1,16
Rise Time (20 to 80%) t+ 15 9 4 15 8 1,16
Fall Time (20 to 80%) t– 15 9 4 15 8 1,16
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
MC10164
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3
APPLICATION INFORMATION
The MC10164 can be used wherever data multiplexing or
parallel to serial conversion is desirable. Full parallel gating
permits equal delays through any data path. The output of
the MC10164 incorporates a buffer gate with eight data
inputs and an enable. A high level on the enable forces the
output low. The MC10164 can be connected directly to a
data bus, due to its open emitter output and output enable.
Figure 1 illustrates how a 1–of–64 line multiplexer can be
built with eight MC10164’s wire ORed at their outputs and
one MC10161 to drive the enables on each multiplexer,
without speed degradation over a single MC10164 being
experienced.
FIGURE 1 — 1–OF–64 LINE MULTIPLEXER
The Bit chosen is dependent on six–bit
code present on inputs 7, 9, 14 of the
MC10161 and the A, B, C inputs of the
MC10164.
Z
out
Z
out
Z
out
Z
out
Z
out
Z
out
ABC
E
MC10164
ABC
E
MC10164
Z
out
ABC
E
MC10164
ABC
E
MC10164
ABC
E
MC10164
ABC
E
MC10164
ABC
E
MC10164
MC10161
Z
out
ABC
MSB
LSB
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
14
9
7
E
MC10164
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