SIGNETICS 10141F
Cross Number:
Item Description:
Circuit Board Hardware - PCBHLSP7-16 V-0 NATURAL
- Category: IC
- Is Military Spec.: No
- Availability: In Stock
- Qty Available: 77
| Qty | Price |
|---|---|
| 1 - 16 | $10.83720 |
| 17 - 32 | $8.45630 |
| 33 - 49 | $7.38900 |
| 50 - 65 | $6.89640 |
| 66 + | $6.40380 |
Technical Document
DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.
Semiconductor Components Industries, LLC, 2002
January, 2002 – Rev. 7
1 Publication Order Number:
MC10141/D
MC10141
Four Bit Universal Shift
Register
The MC10141 is a four–bit universal shift register which performs
shift left, or shift right, serial/parallel in, and serial/parallel out
operations with no external gating. Inputs S1 and S2 control the four
possible operations of the register without external gating of the clock.
The flip–flops shift information on the positive edge of the clock. The
four operations are stop shift, shift left, shift right, and parallel entry of
data. The other six inputs are all data type inputs; four for parallel
entry data, and one for shifting in from the left (DL) and one for
shifting in from the right (DR).
• P
D
= 425 mW typ/pkg (No Load)
• f
Shift
= 200 MHz typ
• t
r
, t
f
= 2.0 ns typ (20%–80%)
LOGIC DIAGRAM
V
CC1
= PIN 1
V
CC2
= PIN 16
V
EE
= PIN 8
Parallel Enter
Shift Right
Shift Left
Hold
D
Q
C
1 of 4
Decode
r
D3
DL
S1
DR
C
Q3
S2
D2 D1 D0
Q2 Q1 Q0
D
Q
C
D
Q
C
D
Q
C
TRUTH TABLE
SELECT OUTPUTS
S1 S2 OPERATING MODE Q0
n+1
Q1
n+1
Q2
n+1
Q3
n+1
L L Parallel Entry D0 D1 D2 D3
L H Shift Right* Q1
n
Q2
n
Q3
n
DR
H L Shift Left* DL Q0
n
Q1
n
Q2
n
H H Stop Shift Q0
n
Q1
n
Q2
n
Q3
n
*Outputs as exist after pulse appears at “C” input with input conditions as
shown. (Pulse = Positive transition of clock input).
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Device Package Shipping
ORDERING INFORMATION
MC10141L CDIP–16 25 Units / Rail
MC10141P PDIP–16 25 Units / Rail
MC10141FN PLCC–20 46 Units / Rail
MARKING
DIAGRAMS
1
16
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
CDIP–16
L SUFFIX
CASE 620
MC10141L
AWLYYWW
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
10141
AWLYYWW
1
1
16
MC10141P
AWLYYWW
DIP PIN ASSIGNMENT
V
CC1
Q2
Q3
C
DR
D3
S2
V
EE
V
CC2
Q1
Q0
DL
D0
D1
S1
D2
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables
on page 18 of the ON Semiconductor MECL Data Book
(DL122/D).
MC10141
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2
SHIFT FREQUENCY TEST CIRCUIT
TEST PROCEDURES:
1.SET D1, D2, D3 = +0.31 VDC (LOGIC L)
D0 = +1.11 VDC (LOGIC H)
2.APPY CLOCK PULSE TO SET Q0 HIGH.
3.MAINTAIN CLOCK LOW.
SET S1 = +0.31 VDC (LOGIC L)
S2 = +1.11 VDC (LOGIC H)
4. TEST SHIFT FREQUENCY
—
V
IH
V
IL
50-ohm termination to ground
located in each scope channel input.
INPUT
DL
Coax
Q3
Q2
Q1
Q0
C
D0
D1
D2
D3
S1
S2
V
OUT
V
IN
COAX
16
25 uF
1
0.1 µF
8
V
EE
= -3.2VDC
V
CC1
= V
CC2
+2.0 VDC
0.1 µF
PULSE GENERATOR
DR
All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should be
< 1/4 inch from TP
in
to input pin and
TP
out
to output pin.
MC10141
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3
ELECTRICAL CHARACTERISTICS
Test Limits
Pin
Under
–30°C +25°C +85°C
Characteristic Symbol
U
n
d
er
Test
Min Max Min Typ Max Min Max
Unit
Power Supply Drain Cur-
rent
I
E
8 112 82 102 112 mAdc
Input Current I
inH
5
6
7
4
350
350
390
425
220
220
245
265
220
220
245
265
µAdc
I
inL
12 0.5 0.5 0.3 µAdc
Output Voltage Logic 1 V
OH
3 –1.060 –0.890 –0.960 –0.810 –0.890 –0.700 Vdc
Output Voltage Logic 0 V
OL
3 –1.890 –1.675 –1.850 –1.650 –1.825 –1.615 Vdc
Threshold Voltage Logic 1 V
OHA
(Note 1.)
3
3
3
3
–1.080
–1.080
–1.080
–1.080
–0.980
–0.980
–0.980
–0.980
–0.910
–0.910
–0.910
–0.910
Vdc
Threshold Voltage Logic 0 V
OLA
(Note 1.)
3
3
3
3
–1.655
–1.655
–1.655
–1.655
–1.630
–1.630
–1.630
–1.630
–1.595
–1.595
–1.595
–1.595
Vdc
Switching Times (50Ω
Load)
ns
Propagation Delay
Setup TIme (t
setup
)
Hold Time (t
hold
)
t
4+3+
t
12+4+
t
10+4+
t
4+12+
3
14
14
14
1.7
2.5
5.5
1.5
3.9 1.8
2.5
5.0
1.5
2.9 3.8 2.0
2.5
5.5
1.5
4.2
Rise Time (20 to 80%) t
3+
3 1.0 3.4 1.1 2.0 3.3 1.1 3.6
Fall Time (20 to 80%) t
3–
3 1.0 3.4 1.1 2.0 3.3 1.1 3.6
Shift Frequency f
shift
150 150 200 150 MHz
1. These tests to be performed in sequence as shown.
V
IH
V
IL
P1
V
IHA
V
IL
P2
V
ILA
V
IL
P3
2. See shift frequency test circuit for test procedures.
3. Reset to zero before performing test.
4. Reset to one before performing test.
