SIGNETICS 10135F

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Item Description: Circuit Board Hardware - PCBHLSP7-06 V-0 NATURAL

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SIGNETICS 8700
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

LOGIC DIAGRAM
V
CC1
= PIN 1
V
CC2
= PIN 16
V
EE
= PIN 8
S1 5
J1
7
K1
6
R1 4
C 9
S2 12
J2
10
K2
11
R2 13
Q1
Q1
Q2
Q2
2
3
15
14
DIP PIN ASSIGNMENT
V
CC1
Q1
Q1
R1
S1
K1
J1
V
EE
V
CC2
Q2
Q2
R2
S2
K2
J2
C
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 18 of the ON Semiconductor MECL
Data Book (DL122/D).
Semiconductor Components Industries, LLC, 2002
January, 2002 – Rev. 7
1 Publication Order Number:
MC10135/D
MC10135
Dual J-K Master-Slave
Flip-Flop
The MC10135 is a dual master–slave dc coupled J–K flip–flop.
Asynchro– nous set (S) and reset (R) are provided. The set and reset
inputs override the clock.
A common clock is provided with separate J–K inputs. When the
clock is static, the J–K inputs do not effect the output.
The output states of the flip–flop change on the positive transition of
the clock.
P
D
= 280 mW typ/pkg (No Load)
f
Tog
= 140 MHz typ
t
pd
= 3.0 ns typ
t
r
, t
f
= 2.5 ns typ (20%–80%)
R–S TRUTH TABLE CLOCK J–K TRUTH TABLE*
R S Q
n+1
J K Q
n+1
L
L
H
H
L
H
L
H
Q
n
H
L
N.D.
L
H
L
H
L
L
H
H
Q
n
L
H
Q
n
N.D. = Not Defined *Output states change on positive
transition of clock for J
–K input
condition present.
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Device Package Shipping
ORDERING INFORMATION
MC10135L CDIP–16 25 Units / Rail
MC10135P PDIP–16 25 Units / Rail
MC10135FN PLCC–20 46 Units / Rail
MARKING
DIAGRAMS
1
16
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
CDIP–16
L SUFFIX
CASE 620
MC10135L
AWLYYWW
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
10135
AWLYYWW
1
1
16
MC10135P
AWLYYWW
MC10135
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2
ELECTRICAL CHARACTERISTICS
Test Limits
Pin
Under
–30°C +25°C +85°C
Characteristic Symbol
U
n
d
er
Test
Min Max Min Typ Max Min Max
Unit
Power Supply Drain Current I
E
8 75 54 68 75 mAdc
Input Current I
inH
6,7,9,10,11
4,5,12,13
425
620
265
390
265
390
µAdc
I
inL
4,5,6,7,9,
10,11,12,13
0.5
0.5
0.5
0.5
0.3
0.3
µAdc
Output Voltage Logic 1 V
OH
2
2 (3.)
–1.060
–1.060
–0.890
–0.890
–0.960
–0.960
–0.810
–0.810
–0.890
–0.890
–0.700
–0.700
Vdc
Output Voltage Logic 0 V
OL
3
3 (3.)
–1.890
–1.890
–1.675
–1.675
–1.850
–1.850
–1.650
–1.650
–1.825
–1.825
–1.615
–1.615
Vdc
Threshold Voltage Logic 1 V
OHA
2
2 (4.)
–1.080
–1.080
–0.980
–0.980
–0.910
–0.910
Vdc
Threshold Voltage Logic 0 V
OLA
3
3 (4.)
–1.655
–1.655
–1.630
–1.630
–1.595
–1.595
Vdc
Switching Times (50 Load)
Clock Input
ns
Propagation Delay t
9+2+
t
9+2–
2
2
1.8
1.8
5.0
5.0
1.8
1.8
3.0
3.0
4.5
4.5
1.8
1.8
4.6
4.6
Rise Time (20 to 80%) t
2+
, t
3+
2, 3 1.1 4.8 1.1 2.0 4.5 1.1 4.7
Fall Time (20 to 80%) t
2–
, t
3–
2, 3 1.1 4.8 1.1 2.0 4.5 1.1 4.7
Set Input ns
Propagation Delay t
5+2+
t
12+15+
t
5+3–
t
12+14–
2
15
3
14
1.8
1.8
1.8
1.8
5.6
5.6
5.6
5.6
1.8
1.8
1.8
1.8
3.0
3.0
3.0
3.0
5.0
5.0
5.0
5.0
1.8 5.2
5.2
5.2
5.2
Reset Input ns
Propagation Delay t
4+2–
t
4+3–
t
13+15–
t
13+14+
2
3
15
14
1.8
1.8
1.8
1.8
5.6
5.6
5.6
5.6
1.8
1.8
1.8
1.8
3.0
3.0
3.0
3.0
5.0
5.0
5.0
5.0
1.8
1.8
1.8
1.8
5.2
5.2
5.2
5.2
Setup Time t
setup
7 2.5 2.5 1.0 2.5 ns
Hold Time t
hold
7 1.5 1.5 1.0 2.5 ns
Toggle Frequency (Max) f
tog
2 125 125 140 125 MHz
1. Individually test each input; apply V
IHmax
to pin under test.
2. Individually test each input; apply V
ILmin
to pin under test.
3. Output level to be measured after a clock pulse has been applied to the C
E
Input (Pin 6)
V
IHmax
V
ILmin
4. Output level to be measured after a clock pulse has been applied to the C
E
Input (Pin 6)
V
IHAmax
V
ILAmin
MC10135
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3
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@ Test Temperature V
IHmax
V
ILmin
V
IHAmin
V
ILAmax
V
EE
–30°C –0.890 –1.890 –1.205 –1.500 –5.2
+25°C –0.810 –1.850 –1.105 –1.475 –5.2
+85°C –0.700 –1.825 –1.035 –1.440 –5.2
Pin
Under
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
(V )
Characteristic Symbol
Under
Test
V
IHmax
V
ILmin
V
IHAmin
V
ILAmax
V
EE
(V
CC
)
Gnd
Power Supply Drain Current I
E
8 8 1, 16
Input Current I
inH
6,7,9,10,11
4,5,12,13
Note 1.
Note 1.
8
8
1, 16
1, 16
I
inL
4,5,6,7,9,
10,11,12,13
Note 2.
Note 2.
8
8
1, 16
1, 16
Output Voltage Logic 1 V
OH
2
2 (3.)
5
6
8
8
1, 16
1, 16
Output Voltage Logic 0 V
OL
3
3 (3.)
5
6
8
8
1, 16
1, 16
Threshold Voltage Logic 1 V
OHA
2
2 (4.)
6
5 8
8
1, 16
1, 16
Threshold Voltage Logic 0 V
OLA
3
3 (4.)
6
5 8
8
1, 16
1, 16
Switching Times (50 Load)
Clock Input
Pulse In Pulse Out –3.2 V +2.0 V
Propagation Delay t
9+2+
t
9+2–
2
2
9
9
2
2
8
8
1, 16
1, 16
Rise Time (20 to 80%) t
2+
, t
3+
2, 3 9 2, 3 8 1, 16
Fall Time (20 to 80%) t
2–
, t
3–
2, 3 9 2, 3 8 1, 16
Set Input
Propagation Delay t
5+2+
t
12+15+
t
5+3–
t
12+14–
2
15
3
14
5
12
5
12
2
15
3
14
8
8
8
8
1, 16
1, 16
1, 16
1, 16
Reset Input
Propagation Delay t
4+2–
t
4+3–
t
13+15–
t
13+14+
2
3
15
14
4
4
13
13
2
3
15
14
8
8
8
8
1, 16
1, 16
1, 16
1, 16
Setup Time t
setup
7 6, 9 2 8 1, 16
Hold Time t
hold
7 6, 9 2 8 1, 16
Toggle Frequency (Max) f
tog
2 9 2 8 1, 16
1. Individually test each input; apply V
IHmax
to pin under test.
2. Individually test each input; apply V
ILmin
to pin under test.
3. Output level to be measured after a clock pulse has been applied to the C
E
Input (Pin 6)
V
IHmax
V
ILmin
4. Output level to be measured after a clock pulse has been applied to the C
E
Input (Pin 6)
V
IHAmax
V
ILAmin
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
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