SIGNETICS 10131F

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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Semiconductor Components Industries, LLC, 2002
January, 2002 – Rev. 7
1 Publication Order Number:
MC10131/D
MC10131
Dual Type D Master-Slave
Flip-Flop
The MC10131 is a dual master–slave type D flip–flop.
Asynchronous Set (S) and Reset (R) override Clock (C
C
) and Clock
Enable (C
E
) inputs. Each flip–flop may be clocked separately by
holding the common clock in the low state and using the enable inputs
for the clocking function. If the common clock is to be used to clock
the flip–flop, the Clock
Enable inputs must be in the low state. In this
case, the enable inputs perform the function of controlling the
common clock.
The output states of the flip–flop change on the positive transition of
the clock. A change in the information present at the data (D) input
will not affect the output information at any other time due to master
slave construction.
P
D
= 235 mW typ/pkg (No Load)
F
Tog
= 160 MHz typ
t
pd
= 3.0 ns typ
t
r
, t
f
= 2.5 ns typ (20%–80%)
LOGIC DIAGRAM
V
CC1
= PIN 1
V
CC2
= PIN 16
V
EE
= PIN 8
S1 5
D1 7
C
E1
6
R1 4
C
C
9
R2 13
C
E2
11
D2 10
S2 12
Q1
Q
1
Q
2
Q2
2
3
14
15
DIP PIN ASSIGNMENT
V
CC1
Q1
Q1
R1
S1
C
E1
D1
V
EE
V
CC2
Q2
Q2
R2
S2
C
E2
D2
C
C
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
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Device Package Shipping
ORDERING INFORMATION
MC10131L CDIP–16 25 Units / Rail
MC10131P PDIP–16 25 Units / Rail
MC10131FN PLCC–20 46 Units / Rail
MARKING
DIAGRAMS
1
16
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
CDIP–16
L SUFFIX
CASE 620
MC10131L
AWLYYWW
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
10131
AWLYYWW
1
1
16
MC10131P
AWLYYWW
CDQ
n+1
CLOCKED TRUTH TABLE
LX Q
n
HL L
HH H
C = C
E
+ C
C.
A clock H is a clock transition from a low to a
high state.
RSQ
n+1
R–S TRUTH TABLE
LH H
HL L
H H N.D.
N.D. = Not Defined
LL Q
n
MC10131
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2
ELECTRICAL CHARACTERISTICS
Test Limits
Pin
Under
–30°C +25°C +85°C
Characteristic Symbol
U
n
d
er
Test
Min Max Min Typ Max Min Max
Unit
Power Supply Drain Current I
E
8 62 45 56 62 mAdc
Input Current I
inH
4
5
6
7
9
525
525
350
390
425
330
330
220
245
265
330
330
220
245
265
µAdc
I
inL
4, 5*
6, 7, 9*
0.5
0.5
0.5
0.5
0.3
0.3
µAdc
Output Voltage Logic 1 V
OH
2
2
–1.060
–1.060
–0.890
–0.890
–0.960
–0.960
–0.810
–0.810
–0.890
–0.890
–0.700
–0.700
Vdc
Output Voltage Logic 0 V
OL
2
3
–1.890
–1.890
–1.675
–1.675
–1.850
–1.850
–1.650
–1.650
–1.825
–1.825
–1.615
–1.615
Vdc
Threshold Voltage Logic 1 V
OHA
2
2
–1.080
–1.080
–0.980
–0.980
–0.910
–0.910
Vdc
Threshold Voltage Logic 0 V
OLA
2
3
–1.655
–1.655
–1.630
–1.630
–1.595
–1.595
Vdc
Switching Times (50 Load)
Clock Input
ns
Propagation Delay t
9+2–
t
9+2+
t
6+2+
t
6+2–
2
2
2
2
1.7
1.7
1.7
1.7
4.6
4.6
4.6
4.6
1.8
1.8
1.8
1.8
3.0
3.0
3.0
3.0
4.5
4.5
4.5
4.5
1.8
1.8
1.8
1.8
5.0
5.0
5.0
5.0
Rise Time (20 to 80%) t
2+
2 1.0 4.6 1.1 2.5 4.5 1.1 4.9
Fall Time (20 to 80%) t
2–
2 1.0 4.6 1.1 2.5 4.5 1.1 4.9
Set Input ns
Propagation Delay t
5+2+
t
12+15+
t
5+3–
t
12+14–
2
15
3
14
1.7
1.7
1.7
1.7
4.4
4.4
4.4
4.4
1.8
1.8
1.8
1.8
2.8
2.8
2.8
2.8
4.3
4.3
4.3
4.3
1.8
1.8
1.8
1.8
4.8
4.8
4.8
4.8
Reset Input ns
Propagation Delay t
4+2–
t
13+15–
t
4+3–
t
13+14+
2
15
3
14
1.7
1.7
1.7
1.7
4.4
4.4
4.4
4.4
1.8
1.8
1.8
1.8
2.8
2.8
2.8
2.8
4.3
4.3
4.3
4.3
1.8
1.8
1.8
1.8
4.8
4.8
4.8
4.8
Setup Time t
setup
7 2.5 2.5 2.5 ns
Hold Time t
hold
7 1.5 1.5 1.5 ns
Toggle Frequency (Max) f
tog
2 125 125 160 125 MHz
* Individually test each input applying V
IH
or V
IL
to input under test.
Output level to be measured after a clock pulse has been applied to the C
E
Input (Pin 6)
V
IHmax
V
ILmin
MC10131
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3
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@ Test Temperature V
IHmax
V
ILmin
V
IHAmin
V
ILAmax
V
EE
–30°C –0.890 –1.890 –1.205 –1.500 –5.2
+25°C –0.810 –1.850 –1.105 –1.475 –5.2
+85°C –0.700 –1.825 –1.035 –1.440 –5.2
Pin
Under
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
(V )
Characteristic Symbol
Under
Test
V
IHmax
V
ILmin
V
IHAmin
V
ILAmax
V
EE
(V
CC
)
Gnd
Power Supply Drain Current I
E
8 8 1, 16
Input Current I
inH
4
5
6
7
9
4
5
6
7
9
8
8
8
8
8
1, 16
1, 16
1, 16
1, 16
1, 16
I
inL
4, 5*
6, 7, 9*
*
*
8
8
1, 16
1, 16
Output Voltage Logic 1 V
OH
2
2
5
7
8
8
1, 16
1, 16
Output Voltage Logic 0 V
OL
2
3
5
7
8
8
1, 16
1, 16
Threshold Voltage Logic 1 V
OHA
2
2
5
7
9
8
8
1, 16
1, 16
Threshold Voltage Logic 0 V
OLA
2
3
5
7
9
8
8
1, 16
1, 16
Switching Times (50 Load)
Clock Input
+1.11Vdc Pulse In Pulse Out –3.2 V +2.0 V
Propagation Delay t
9+2–
t
9+2+
t
6+2+
t
6+2–
2
2
2
2
7
7
9
9
6
6
2
2
2
2
8
8
8
8
1, 16
1, 16
1, 16
1, 16
Rise Time (20 to 80%) t
2+
2 7 9 2 8 1, 16
Fall Time (20 to 80%) t
2–
2 9 2 8 1, 16
Set Input
Propagation Delay t
5+2+
t
12+15+
t
5+3–
t
12+14–
2
15
3
14
6
9
5
12
5
12
2
15
3
14
8
8
8
8
1, 16
1, 16
1, 16
1, 16
Reset Input
Propagation Delay t
4+2–
t
13+15–
t
4+3–
t
13+14+
2
15
3
14
6
9
4
13
4
13
2
15
3
14
8
8
8
8
1, 16
1, 16
1, 16
1, 16
Setup Time t
setup
7 6, 7 2 8 1, 16
Hold Time t
hold
7 6, 7 2 8 1, 16
Toggle Frequency (Max) f
tog
2 6 2 8 1, 16
* Individually test each input applying V
IH
or V
IL
to input under test.
Output level to be measured after a clock pulse has been applied to the C
E
Input (Pin 6)
V
IHmax
V
ILmin
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
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