SIGNETICS 10104F

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SIGNETICS 8600
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Semiconductor Components Industries, LLC, 2002
January, 2002 – Rev. 7
1 Publication Order Number:
MC10104/D
MC10104
Quad 2-Input AND Gate
The MC10104 is a quad 2–input AND gate. One of the gates has
both AND/NAND outputs available.
P
D
= 35 mW typ/gate (No Load)
t
pd
= 2.7 ns typ
t
r
, t
f
= 2.0 ns typ (20%–80%)
LOGIC DIAGRAM
V
CC1
= PIN 1
V
CC2
= PIN 16
V
EE
= PIN 8
14
13
12
11
10
3
7
6
2
5
4
9
15
DIP
PIN ASSIGNMENT
V
CC1
A
OUT
B
OUT
A
IN
A
IN
B
IN
B
IN
V
EE
V
CC2
D
OUT
C
OUT
D
IN
D
IN
C
IN
C
IN
D
OUT
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
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Device Package Shipping
ORDERING INFORMATION
MC10104L CDIP–16 25 Units / Rail
MC10104P PDIP–16 25 Units / Rail
MC10104FN PLCC–20 46 Units / Rail
MARKING
DIAGRAMS
1
16
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
CDIP–16
L SUFFIX
CASE 620
MC10104L
AWLYYWW
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
10104
AWLYYWW
1
1
16
MC10104P
AWLYYWW
MC10104
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2
ELECTRICAL CHARACTERISTICS
Test Limits
Pin
Under
–30°C +25°C +85°C
Characteristic Symbol
U
n
d
er
Test
Min Max Min Typ Max Min Max
Unit
Power Supply Drain Current I
E
8 39 35 39 mAdc
Input Current I
inH
* 12
13
425
350
265
220
265
220
µAdc
I
inL
12 0.5 0.5 0.3 µAdc
Output Voltage Logic 1 V
OH
15
9
–1.060
–1.060
–0.890
–0.890
–0.960
–0.960
–0.810
–0.810
–0.890
–0.890
–0.700
–0.700
Vdc
Output Voltage Logic 0 V
OL
15
9
–1.890
–1.890
–1.675
–1.675
–1.850
–1.850
–1.650
–1.650
–1.825
–1.825
–1.615
–1.615
Vdc
Threshold Voltage Logic 1 V
OHA
9
9
15
15
–1.090
–1.090
–1.090
–1.090
–0.980
–0.980
–0.980
–0.980
–0.910
–0.910
–0.910
–0.910
Vdc
Threshold Voltage Logic 0 V
OLA
9
9
15
15
–1.655
–1.655
–1.655
–1.655
–1.630
–1.630
–1.630
–1.630
–1.595
–1.595
–1.595
–1.595
Vdc
Switching Times (50 Load) ns
Propagation Delay t
12+15+
t
12–15–
t
12+9–
t
12–9+
15
15
9
9
1.0
1.0
1.0
1.0
4.3
4.3
4.3
4.3
1.0
1.0
1.0
1.0
2.2
2.2
2.2
2.2
4.0
4.0
4.0
4.0
1.0
1.0
1.0
1.0
4.2
4.2
4.2
4.2
t
13+15+
t
13+9–
15
9
1.0
1.0
4.3
4.3
1.0
1.0
2.7
2.7
4.0
4.0
1.0
1.0
4.2
4.2
Rise Time (20 to 80%) t
15+
t
9+
15
9
1.5
1.5
3.7
3.7
1.5
1.5
2.0
2.0
3.5
3.5
1.5
1.5
3.6
3.6
Fall Time (20 to 80%) t
15–
t
9–
15
9
1.5
1.5
3.7
3.7
1.5
1.5
2.0
2.0
3.5
3.5
1.5
1.5
3.6
3.6
* Inputs 4, 7, 10 and 13 will behave similarly for ac and I
inH
values.
Inputs 5, 6, 11 and 12 will behave similarly for ac and I
inH
values.
MC10104
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3
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@ Test Temperature V
IHmax
V
ILmin
V
IHAmin
V
ILAmax
V
EE
–30°C –0.890 –1.890 –1.205 –1.500 –5.2
+25°C –0.810 –1.850 –1.105 –1.475 –5.2
+85°C –0.700 –1.825 –1.035 –1.440 –5.2
Pin
Under
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
(V )
Characteristic Symbol
Under
Test
V
IHmax
V
ILmin
V
IHAmin
V
ILAmax
V
EE
(V
CC
)
Gnd
Power Supply Drain Current I
E
8 8 1, 16
Input Current I
inH*
12
13
12, 13
13
8
8
1, 16
1, 16
I
inL
12 12 8 1, 16
Output Voltage Logic 1 V
OH
15
9
12, 13 8
8
1, 16
1, 16
Output Voltage Logic 0 V
OL
15
9
12, 13
8
8
1, 16
1, 16
Threshold Voltage Logic 1 V
OHA
9
9
15
15
12
13
13
12
12
13
8
8
8
8
1, 16
1, 16
1, 16
1, 16
Threshold Voltage Logic 0 V
OLA
9
9
15
15
12
13
13
12
12
13
8
8
8
8
1, 16
1, 16
1, 16
1, 16
Switching Times (50 Load) +1.11V Pulse In Pulse Out –3.2 V +2.0 V
Propagation Delay t
12+15+
t
12–15–
t
12+9–
t
12–9+
15
15
9
9
13
13
13
13
12
12
12
12
15
15
9
9
8
8
8
8
1, 16
1, 16
1, 16
1, 16
t
13+15+
t
13+9–
15
9
12
12
13
13
15
9
8
8
1, 16
1, 16
Rise Time (20 to 80%) t
15+
t
9+
15
9
12
12
13
13
15
9
8
8
1, 16
1, 16
Fall Time (20 to 80%) t
15–
t
9–
15
9
12
12
13
13
15
9
8
8
1, 16
1, 16
* Inputs 4, 7, 10 and 13 will behave similarly for ac and I
inH
values.
Inputs 5, 6, 11 and 12 will behave similarly for ac and I
inH
values.
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
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