
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 11
1 Publication Order Number:
MC100LVEL90/D
MC100LVEL90
−3.3V / −5VTriple ECL Input
to LVPECL Output Translator
Description
The MC100LVEL90 is a triple ECL to LVPECL translator. The device
receives either −3.3 V or −5 V differential ECL signals, determined by the
V
EE
supply level, and translates them to +3.3 V differential LVPECL
output signals.
To accomplish the level translation, the LVEL90 requires three power
rails. The V
CC
supply should be connected to the positive supply, and the
V
EE
pin should be connected to the negative power supply. The GND
pins, as expected, are connected to the system ground plane. Both V
EE
and V
CC
should be bypassed to ground via 0.01 mF capacitors.
Under open input conditions, the D input will be biased at V
EE
/2 and
the D input will be pulled to V
EE
. This condition will force the Q output
to a LOW, ensuring stability.
The V
BB
pin, an internally generated voltage supply, is available to this
device only. For single-ended input conditions, the unused differential
input is connected to V
BB
as a switching reference voltage. V
BB
may also
rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a
0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When
not used, V
BB
should be left open.
Features
• 500 ps Propagation Delays
• ESD Protection: >2 kV HBM, >200 V MM
• The 100 Series Contains Temperature Compensation
• Operating Range: V
CC
= 3.0 V to 3.8 V;
V
EE
= −3.0 V to −5.5 V; GND = 0 V
• Internal Input Pulldown Resistors
• Q Output will Default LOW with Inputs Open or at V
EE
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity;
Pb Pkg Level 1,
Pb−Free Pkg Level 3
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 261 devices
• Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
*For additional marking information, refer to
Application Note AND8002/D.
MARKING DIAGRAM*
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
SO−20 WB
DW SUFFIX
CASE 751D
20
1
100LVEL90
AWLYYWWG