Name: 5P10
SKU: 5P10
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or modifications due to changes in technical specifications.

EN25P10

Rev. C, Issue Date: 2007

Read Status Register (RDSR) (05h)

The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register

may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress.

When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit

before sending a new instruction to the device. It is also possible to read the Status Register continuously,

as shown in Figure 7.

Table 6. Status Register Bit Locations

SRP 0 0 0 BP1 BP0 WEL BUSY

The status and control bits of the Status Register are as follows:

BUSY bit. The BUSY bit indicates whether the memory is busy with a Write Status Register, Program or

Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress.

WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When

set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and

no Write Status Register, Program or Erase instruction is accepted.

BP1, BP0 bits. The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be

software protected against Program and Erase instructions. These bits are written with the Write Status

relevant memory area (as defined in Table 3.) becomes protected against Page Program (PP) and Sector

Erase (SE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the Hardware

Protected mode has not been set. The Bulk Erase (BE) instruction is executed if, and only if, both Block

Protect (BP1, BP0) bits are 0.

Reserved bit. Status register bit locations 5 and 6 are reserved for future use. Current devices will read 0

for these bit locations. It is recommended to mask out the reserved bit when testing the Status Register.

Doing this will ensure compatibility with future devices.

SRP bit. The Status Register Protect (SRP) bit is operated in conjunction with the Write Protect (WP#)

signal. The Status Register Write Protect (SRP) bit and Write Protect (WP#) signal allow the device to be

put in the Hardware Protected mode (when the Status Register Protect (SRP) bit is set to 1, and Write

Protect (WP#) is driven Low). In this mode, the non-volatile bits of the Status Register (SRP, BP1, BP0)

become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for

execution.

Status Register Protect

Reserved Bits Block Protect Bits

Write Enable Latch

Busy

or modifications due to changes in technical specifications.

EN25P10

Rev. C, Issue Date: 2007

Write Status Register (WRSR) (01h)

The Write Status Register (WRSR) instruction allows new values to be written to the Status Register.

Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After

the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable

Latch (WEL).

The Write Status Register (WRSR) instruction is entered by driving Chip Select (CS#) Low, followed by

the instruction code and the data byte on Serial Data Input (DI).

The instruction sequence is shown in Figure 8.. The Write Status Register (WRSR) instruction has no

effect on S6, S5, S1 and S0 of the Status Register. S6 and S5 are always read as 0. Chip Select (CS#)

must be driven High after the eighth bit of the data byte has been latched in. If not, the Write Status

Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in

progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The

Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is

completed. When the cycle is completed, the Write Enable Latch (WEL) is reset.

The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect

(BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table 3..

The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register

Protect (SRP) bit in accordance with the Write Protect (WP#) signal. The Status Register Protect (SRP)

bit and Write Protect (WP#) signal allow the device to be put in the Hardware Protected Mode (HPM). The

Write Status Register (WRSR) instruction is not executed once the Hardware Protected Mode (HPM) is

entered.

or modifications due to changes in technical specifications.

EN25P10

Rev. C, Issue Date: 2007

Read Data Bytes (READ) (03h)

The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read Data

Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the

rising edge of Serial Clock (CLK). Then the memory contents, at that address, is shifted out on Serial Data

Output (DO), each bit being

shifted out, at a maximum frequency f

, during the falling edge of Serial Clock

(CLK).

The instruction sequence is shown in Figure 9.. The first byte addressed can be at any location. The

address is automatically incremented to the next higher address after each byte of data is shifted out. The

whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the

highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be

continued indefinitely.

The Read Data Bytes (READ) instruction is terminated by driving Chip Select (CS#) High. Chip Select

(CS#) can be driven High at any time during data output. Any Read Data Bytes (READ) instruction, while

an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is

in progress.

Read Data Bytes at Higher Speed (FAST_READ) (0Bh)

The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read Data

Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-A0) and a dummy

byte, each bit being latched-in during the rising edge of Serial Clock (CLK). Then the memory contents, at

that address, is shifted out on Serial Data Output (DO), each bit being shifted out, at a maximum

frequency F

, during the falling edge of Serial Clock (CLK).

The instruction sequence is shown in Figure 10.. The first byte addressed can be at any location. The

address is automatically incremented to the next higher address after each byte of data is shifted out. The

whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ)

instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the

read sequence to be continued indefinitely.

The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving Chip Select

(CS#) High. Chip Select (CS#) can be driven High at any time during data output. Any Read Data Bytes at

Higher Speed (FAST_READ) instruction, while an Erase, Program or Write cycle is in progress, is

rejected without having any effects on the cycle that is in progress.

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5P10

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