Name: 5P10
SKU: 5P10
Price: 30.00000 USD
Availability: OutOfStock

or modifications due to changes in technical specifications.

EN25P10

Rev. C, Issue Date: 2007

FEATURES

• Single power supply operation

- Full voltage range: 2.7-3.6 volt

• 1 M-bit Serial Flash

- 1 M-bit/128 K-byte/512 pages

- 256 bytes per programmable page

• High performance

- 100MHz clock rate

• Low power consumption

- 5 mA typical active current

- 1 μA typical power down current

• Uniform Sector Architecture:

- Four 32-Kbyte sectors

• Software and Hardware Write Protection:

- Write Protect all or portion of memory via

software

- Enable/Disable protection with WP# pin

• High performance program/erase speed

- Byte program time: 7µs typical

- Page program time: 1.5ms typical

- Sector erase time: 500 ms typical

- Chip erase time: 2 Seconds typical

• Minimum 100K endurance cycle

• Package Options

- 8 pins SOP 150mil body width

- 8 contact VDFN

- All Pb-free packages are RoHS compliant

• Commercial and industrial temperature

Range

GENERAL DESCRIPTION

The EN25P10 is a 1M-bit (128K-byte) Serial Flash memory, with advanced write protection

mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to

256 bytes at a time, using the Page Program instruction.

The EN25P10 is designed to allow either single Sector at a time or full chip erase operation. The

EN25P10 can be configured to protect part of the memory as the software protected mode. The

device can sustain a minimum of 100K program/erase cycles on each sector.

EN25P10

1 Mbit Uniform Sector, Serial Flash Memory

or modifications due to changes in technical specifications.

EN25P10

Rev. C, Issue Date: 2007

Figure.1 CONNECTION DIAGRAMS

Figure 2. BLOCK DIAGRAM

8 - LEAD SOP 8 - CONTACT VDFN

or modifications due to changes in technical specifications.

EN25P10

Rev. C, Issue Date: 2007

SIGNAL DESCRIPTION

Serial Data Input (DI)

The SPI Serial Data Input (DI) pin provides a means for instructions, addresses and data to be

serially written to (shifted into) the device. Data is latched on the rising edge of the Serial Clock (CLK)

input pin.

Serial Data Output (DO)

The SPI Serial Data Output (DO) pin provides a means for data and status to be serially read from

(shifted out of) the device. Data is shifted out on the falling edge of the Serial Clock (CLK) input pin.

Serial Clock (CLK)

The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See

SPI Mode")

Chip Select (CS#)

The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device

is deselected and the Serial Data Output (DO) pin is at high impedance. When deselected, the

devices power consumption will be at standby levels unless an internal erase, program or status

consumption will increase to active levels and instructions can be written to and data read from the

device. After power-up, CS# must transition from high to low before a new instruction will be

accepted.

Hold (HOLD#)

The HOLD pin allows the device to be paused while it is actively selected. When HOLD is brought

low, while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will

be ignored (don’t care). The hold function can be useful when multiple devices are sharing the same

SPI signals.

Write Protect (WP#)

The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in

conjunction with the Status Register’s Block Protect (BP0, BP1) bits and Status Register Protect

(SRP) bits, a portion or the entire memory array can be hardware protected.

Table 1. PIN Names

Symbol Pin Name

CLK Serial Clock Input

DI Serial Data Input

DO Serial Data Output

CS# Chip Enable

WP# Write Protect

HOLD# Hold Input

Vcc Supply Voltage (2.7-3.6V)

Vss Ground

Part #	5P10
Description
Category	IC
Availability	Out of Stock
Qty	0

5P10

Related Items

Technical Document