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AD10242BZ

Part # AD10242BZ
Description
Category HYBRID
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
AD10242
FEATURES
Two Matched ADCs with Input Signal Conditioning
Selectable Bipolar Input Voltage Range
(60.5 V, 61.0 V, 62.0 V)
Full MIL-STD-883B Compliant
80 dB Spurious-Free Dynamic Range
Trimmed Channel-Channel Matching
APPLICATIONS
Radar Processing
Communications Receivers
FLIR Processing
Secure Communications
Any I/Q Signal Processing Application
The AD10242 operates with ±5.0 V for the analog signal condi-
tioning with a separate +5.0 V supply for the analog-to-digital
conversion. Each channel is completely independent allowing
operation with independent encode or analog inputs. The
AD10242 also offers the user a choice of analog input signal
ranges to minimize additional signal conditioning required for
multiple functions within a single system. The heart of the
AD10242 is the AD9042 which is designed specifically for appli-
cations requiring wide dynamic range.
The AD10242 is manufactured by Analog Devices on our
MIL-PRF-38534 MCM line and is completely qualified. Units
are packaged in a custom cofired ceramic 68-lead gull wing
package and specified for operation from –55°C to +125°C.
Contact the factory for additional custom options including
those which allow the user to ac couple the ADC directly, by-
passing the front end amplifier section. Also see the AD9042
data sheet for additional details on ADC performance.
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate of 40 MSPS.
2. Dynamic performance specified over entire Nyquist band;
spurious signals @ 80 dBc for –1 dBFS input signals.
3. Low power dissipation: <2 W off ±5.0 V supplies.
4. User defined input amplitude.
5. Packaged in 68-lead ceramic leaded chip carrier.
PRODUCT DESCRIPTION
The AD10242 is a complete dual signal chain solution including
onboard amplifiers, references, ADCs, and output buffering pro-
viding unsurpassed total system performance. Each channel is
laser trimmed for gain and offset matching and provides channel-
to-channel crosstalk performance better than 80 dB. The AD10242
utilizes two each of the AD9631, OP279, and the AD9042 in a
custom MCM to gain space, performance, and cost advantages
over solutions previously available.
FUNCTIONAL BLOCK DIAGRAM
OP279
OP279
AD9042
AD9631
9
12
TIMING
A
IN
3
A
IN
2A
IN
1
D11B (MSB)
D10B
D9B
D8B
D7B
D0B
(LSB)
D1B D2B D3B D4B D5B D6B
D9A
D10A
D11A
(MSB)
(LSB) D0A
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D8A
ENC
ENC
AD10242
5
V
REF
OUTPUT BUFFERING
UNEG
UCOM
UPOS
OP279
OP279
AD9042
AD9631
7
12
TIMING
A
IN
2
A
IN
1
V
REF
OUTPUT BUFFERING
A
IN
3
UPOSUNEG UCOM
ENC
ENC
68
7
626356 55 6457
19
20
21
22
23
24
25
17
18
12
3
4
28
29
31
32
33 36
40
41
42
38
37
39
52
51
49
48
47
46
45
Dual, 12-Bit, 40 MSPS MCM A/D Converter
with Analog Input Signal Conditioning
a
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703 © Analog Devices, Inc., 1997
REV. A
–2–
AD10242–SPECIFICATIONS
Electrical Characteristics
(AV
CC
= +5 V; AV
EE
= –5.0 V; DV
CC
= +5 V; applies to each ADC unless otherwise noted)
Test Mil AD10242BZ/TZ
Parameter Temp Level Subgroup Min Typ Max Units
RESOLUTION 12 Bits
DC ACCURACY
No Missing Codes Full VI 1, 2, 3 Guaranteed
Offset Error +25°C I 1 –0.5 ±0.05 +0.5 % FS
Full VI 2, 3 –2.0 ±1.0 +2.0 % FS
Offset Error Channel Match Full V ±0.1 %
Gain Error
1
+25°C I 1 –1.0 ±0.5 +1.0 % FS
Full VI 2, 3 –1.5 ±0.8 +1.5 % FS
Gain Error Channel Match Full V ±0.1 %
ANALOG INPUT (A
IN
)
Input Voltage Range
A
IN
1 Full I ±0.5 V
A
IN
2 Full I ±1.0 V
A
IN
3 Full I ±2V
Input Resistance
A
IN
1 Full IV 12 99 100 101
A
IN
2 Full IV 12 198 200 202
A
IN
3 Full IV 12 396 400 404
Input Capacitance
2
+25°C IV 12 0 4.0 7.0 pF
Analog Input Bandwidth
3
Full V 60 MHz
ENCODE INPUT
4, 5
Logic Compatibility TTL/CMOS
Logic “1” Voltage Full I 1, 2, 3 2.0 5.0 V
Logic “0” Voltage Full I 1, 2, 3 0 0.8 V
Logic “1” Current (V
INH
= 5 V) Full I 1, 2, 3 625 800 µA
Logic “0” Current (V
INL
= 0 V) Full I 1, 2, 3 –400 –300 µA
Input Capacitance +25°C V 12 7.0 pF
SWITCHING PERFORMANCE
Maximum Conversion Rate
6
Full VI 4, 5, 6 40 50 MSPS
Minimum Conversion Rate
6
Full V 12 5 MSPS
Aperture Delay (t
A
) +25°C V 1.0 ns
Aperture Delay Matching +25°CV ±2.0 ns
Aperture Uncertainty (Jitter) +25°C V 1 ps rms
ENCODE Pulse Width High +25°CIV 12 12 10 ns
ENCODE Pulse Width Low +25°CIV 12 10 41 ns
Output Delay (t
OD
) Full IV 12 10 12 14 ns
SNR
7
Analog Input @ 1.2 MHz +25°CV 68 dB
@ 4.85 MHz +25°CI 4 63 66 dB
Full II 5, 6 62 66 dB
@ 9.9 MHz +25°CI 4 63 65 dB
Full II 5, 6 62 65 dB
@ 19.5 MHz +25°CI 4 60 63 dB
Full II 5, 6 59 62 dB
SINAD
8
Analog Input @ 1.2 MHz +25°CV 67 dB
@ 4.85 MHz +25°CI 4 62 65 dB
Full II 5, 6 61 64 dB
@ 9.9 MHz +25°CI 4 60 64 dB
Full II 5, 6 60 63 dB
@ 19.5 MHz +25°CI 4 58 61 dB
Full II 5, 6 58 60 dB
Test Mil AD10242BZ/TZ
Parameter Temp Level Subgroup Min Typ Max Units
SPURIOUS-FREE DYNAMIC RANGE
9
Analog Input @ 1.2 MHz +25°C I 81 dBFS
@ 4.85 MHz +25°C I 4 70 80 dBFS
Full II 5, 6 70 79 dBFS
@ 9.9 MHz +25°C I 4 63 70 dBFS
Full II 5, 6 63 69 dBFS
@ 19.5 MHz +25°C I 4 60 67 dBFS
Full II 5, 6 60 66 dBFS
TWO-TONE IMD REJECTION
10
F1, F2 @ –7 dBFS Full II 4, 5, 6 70 76 dBc
CHANNEL-TO-CHANNEL ISOLATION
11
+25°CIV 12 75 80 dB
TRANSIENT RESPONSE +25°CV 10 ns
LINEARITY
Differential Nonlinearity +25°C IV 12 0.3 1.0 LSB
(Encode = 20 MHz) Full IV 12 0.5 1.25 LSB
Integral Nonlinearity +25°C V 0.3
LSB
(
Encode
= 20 MHz) Full V 0.5 LSB
OVERVOLTAGE RECOVERY TIME
12
V
IN
= 2.0 × FS Full IV 12 50 100 ns
V
IN
= 4.0 × FS
Full IV 12 75 200 ns
DIGITAL OUTPUTS
Logic Compatibility CMOS
Logic “1” Voltage
13
Full I 1, 2, 3 3.5 4.2 V
Logic “0” Voltage
14
Full I 1, 2, 3 0.45 0.65 V
Output Coding Twos Complement
POWER SUPPLY
AV
CC
Supply Voltage Full VI +5.0 V
I (AV
CC
) Current Full V 260 mA
AV
EE
Supply Voltage Full VI –5.0 V
I (AV
EE
) Current Full V 55 mA
DV
CC
Supply Voltage Full VI +5.0 V
I (DV
CC
) Current Full V 25 mA
I
CC
(Total) Supply Current Full I 1, 2, 3 350 400 mA
Power Dissipation (Total) Full I 1, 2, 3 1.75 2.0 W
Power Supply Rejection Ratio (PSRR) Full I 7, 8 0.01 0.02 % FSR/% V
S
Pass Band Ripple to 10 MHz Full IV 12 0.2 dB
NOTES
1
Gain tests are performed on A
IN
3 over specified input voltage range.
2
Input capacitance specifications combines AD9631 die capacitance + ceramic package capacitance.
3
Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB.
4
ENCODE (Pin 4) driven by single-ended source; ENCODE (Pin 5) bypassed to ground through 0.01 µF capacitor.
5
ENCODE (Pin 4) may also be driven differentially in conjunction with ENCODE (Pin 5); see “Encoding the AD10242” for details.
6
Minimum and maximum conversion rates allow for variation in
Encode
Duty Cycle of 50% ± 5%.
7
Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first 5 harmonics removed).
Encode
= 40.0 MSPS.
8
Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics.
Encode
= 40.0 MSPS.
9
Analog Input signal equal –1 dBFS; SFDR is ratio of converter full scale to worst spur.
10
Both input tones at –7 dBFS; two tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst 3rd order intermod product. f1 = 10.0 MHz
± 100 kHz, 50 kHz f1 – f2 300 kHz.
11
Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B channel (AIN1).
12
Input driven to 2× and 4× A
IN
1 range for >4 clock cycles. Output recovers inband in specified time with
Encode
= 40 MSPS. No foldover guaranteed.
13
Outputs are sourcing 10 µA.
14
Outputs are sinking 10 µA.
All specifications guaranteed within 100 ms of initial power up regardless of sequencing.
Specifications subject to change without notice.
AD10242
–3–
REV. A
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