Description

The ICX054BK is an interline CCD solid-state image

sensor suitable for NTSC color video cameras.

Compared with the current product ICX054AK,

sensitivity is improved drastically through the adoption

of Super HAD CCD technology. Ye, Cy, Mg, and G

complementary color mosaic filters are used.

This chip features a field period readout system, and

an electronic shutter with variable charge-storage

time.

Features

• High sensitivity (+3dB at F5.6, +1.5dB at F1.2 compared with ICX054AK)

• High saturation signal (+1dB compared with ICX054AK)

• Low smear and low dark current

• Excellent antiblooming characteristics

• Continuous variable-speed shutter

• Ye, Cy, Mg and G complementary color mosaic filters on chip

• Horizontal register: 5V drive

• Reset gate: 5V drive

Device Structure

• Interline CCD image sensor

• Image size: Diagonal 6mm (Type 1/3)

• Number of effective pixels: 510 (H) × 492 (V) approx. 250K pixels

• Number of total pixels: 537 (H) × 505 (V) approx. 270K pixels

• Chip size: 6.00mm (H) × 4.96mm (V)

• Unit cell size: 9.6µm (H) × 7.5µm (V)

• Optical black: Horizontal (H) direction: Front 2 pixels, Rear 25 pixels

Vertical (V) direction: Front 12 pixels, Rear 1 pixel

• Number of dummy bits: Horizontal 16

Vertical 1 (even field only)

• Substrate material: Silicon

– 1 –

ICX054BK

E98222A99

Diagonal 6mm (Type 1/3) CCD Image Sensor for NTSC Color Video Cameras

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by

any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the

operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

16 pin DIP (Plastic)

Pin 1

Pin 9

Optical black position

(Top View)

∗

Super HAD CCD is a registered trademark of Sony Corporation. Super HAD CCD is a CCD that drastically improves sensitivity by introducing newly

developed semiconductor technology by Sony Corporation into Sony's high-performance HAD (Hole-Accumulation Diode) sensor.

– 2 –

ICX054BK

Substrate voltage SUB – GND

VDD, VOUT, VSS – GND

Supply voltage

VDD, VOUT, VSS – SUB

Vφ1, Vφ2, Vφ3, Vφ4 – GND

Vertical clock input voltage

Vφ1, Vφ2, Vφ3, Vφ4 – SUB

Voltage difference between vertical clock input pins

Voltage difference between horizontal clock input pins

Hφ1, Hφ2 – Vφ4

Hφ1, Hφ2, RG, VGG – GND

Hφ1, Hφ2, RG, VGG – SUB

VL – SUB

Vφ1, Vφ2, Vφ3, Vφ4, VDD, VOUT – VL

RG – VL

VGG, Vss, Hφ1, Hφ2 – VL

Storage temperature

Operating temperature

Pin No. Symbol Description Pin No. Symbol Description

Vφ4

Vφ3

Vφ2

Vφ1

GND

VGG

VSS

VOUT

Vertical register transfer clock

GND

Output amplifier gate bias

Output amplifier source

Signal output

VDD

GND

SUB

Hφ1

Hφ2

Output amplifier drain supply

GND

Substrate (Overflow drain)

Protective transistor bias

Reset gate clock

Horizontal register transfer clock

Pin Description

14 15

Note

Note) : Photo sensor

OUT

GND

Vφ

GND

SUB

Hφ

Horizontal register

Vertical register

Block Diagram and Pin Configuration

(Top View)

Item

–0.3 to +55

–0.3 to +18

–55 to +10

–15 to +20

to +10

to +15

to +17

–17 to +17

–10 to +15

–55 to +10

–65 to +0.3

–0.3 to +30

–0.3 to +24

–0.3 to +20

–30 to +80

–10 to +60

°C

∗1

Ratings Unit Remarks

Absolute Maximum Ratings

∗1

+27V (Max.) when clock width < 10µs, clock duty factor < 0.1%.

– 3 –

ICX054BK

Item

VDD

VGG

VSS

VSUB

∆VSUB

VRGL

∆VRGL

14.55

1.75

9.0

–3

1.0

–3

15.0

2.0

∗2

15.45

2.25

18.5

4.0

±5%

∗1

Symbol Min. Typ. Max. Unit Remarks

Bias Conditions

DC Characteristics

Grounded with

680Ω resistor

Item

Output amplifier drain current

Input current

IDD

IIN1

IIN2

µA

∗3

∗4

Symbol Min. Typ. Max. Unit Remarks

Output amplifier drain voltage

Output amplifier gate voltage

Output amplifier source

Substrate voltage adjustment range

Fluctuation range after substrate voltage adjustment

Reset gate clock voltage adjustment range

Fluctuation range after reset gate clock voltage adjustment

Protective transistor bias

∗1

Indications of substrate voltage (VSUB) · reset gate clock voltage (VRGL) setting value.

The setting values of substrate voltage and reset gate clock voltage are indicated on the back of the image

sensor by a special code. Adjust substrate voltage (VSUB) and reset gate clock voltage (VRGL) to the

indicated voltage. Fluctuation range after adjustment is ±3%.

VSUB code one character indication

VRGL code one character indication ↑ ↑

VRGL code VSUB code

Code and optimal setting correspond to each other as follows.

VRGL code

Optimal setting 1.0 1.5 2.0 2.5 3.0 3.5 4.0

4 5

VSUB code

Optimal setting

9.0 9.5

10.0 10.511.0 11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 17.0 17.5 18.0 18.5

E f G

h J K L

N P

U V W X

<Example> “5L” → VRGL = 3.0V

VSUB = 12.0V

∗2

VL setting is the VVL voltage of the vertical transfer clock waveform.

∗3

1) Current to each pin when 18V is applied to VDD, VOUT, Vss and SUB pins, while pins that are not tested

are grounded.

2) Current to each pin when 20V is applied sequentially to Vφ1, Vφ2, Vφ3 and Vφ4 pins, while pins that are

not tested are grounded. However, 20V is applied to SUB pin.

3) Current to each pin when 15V is applied sequentially to RG, Hφ1, Hφ2 and VGG pins, while pins that are

not tested are grounded. However, 15V is applied to SUB pin.

4) Current to VL pin when 30V is applied to Vφ1, Vφ2, Vφ3, Vφ4, VDD and VOUT pins or when, 24V is applied

to RG pin or when, 20V is applied to VGG, Vss, Hφ1 and Hφ2 pins, while VL pin is grounded. However,

GND and SUB pins are left open.

∗4

Current to SUB pin when 55V is applied to SUB pin, while pins that are not tested are grounded.

Part #	X0-54B
Description	2.4576 M
Category	CRYSTAL
Availability	In Stock
Qty	21

X0-54B

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Technical Document