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CS5014-BP14

Part # CS5014-BP14
Description A/D Converter 16, 14 & 12-BitSelf-Calibrating, 40pin PDip
Category CONVERTER
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

peaking in its output impedance characteristic at
signal frequencies or their harmonics.
A large capacitor connected between VREF and
AGND can provide sufficiently low output im-
pedance at the high end of the frequency
spectrum, while almost all precision references
exhibit extremely low output impedance at dc.
The magnitude of the current load on the external
reference circuitry will scale to the CLKIN fre-
quency. At full speed, the reference must supply a
maximum load current of 10
µ
A peak-to-peak
(1
µ
A typical). For the CS5012A an output im-
pedance of 15
will therefore yield a maximum
error of 150 mV. With a 2.5V reference and LSB
size of 600 mV, this would insure better than 1/4
LSB accuracy. A 1
µ
F capacitor exhibits an im-
pedance of less than 15
at frequencies greater
than 10 kHz. Similarly, for the CS5014 with a
4.5V reference (275
µ
V/LSB), better than
1/4 LSB accuracy can be insured with an output
impedance of 4
or less (maximum error of
40
µ
V). A 2.2
µ
F capacitor exhibits an imped-
ance of less than 4
at frequencies greater than
5kHz. For the CS5016 with a 4.5V reference
(69
µ
V/LSB), better than 1/4 LSB accuracy can
be insured with an output impedance of less than
2
(maximum error of 20
µ
V). A 20
µ
F capaci-
tor exhibits an impedance of less than 2
at
frequencies greater than 16 kHz. A high-quality
tantalum capacitor in parallel with a smaller ce-
ramic capacitor is recommended.
CLKIN
EOC
Status
EOT
HOLD
SCLK
SDATA
t
d
t
d
Determined
LSB
Fine Charge
Determined
MSB
Determined
MSB - 1
Determined
MSB - 2
Coarse Charge
LSB+1 LSB MSB
MSB - 1
LSB+2
246
8
10 12646260 80/076 787472706866
CS5016:
246
8
10 125654 72/068 70666462605852
CS5014:
246
8
10 12484644 64/060 625856545250
CS5012A:
Figure 9. Serial Output Timing
Notes: 1. Synchronous (loopback) mode is illustrated. After
EOC falls the converter goes into coarse charge mode for
6 CLKIN cycles, then to fine charge mode for 9 cycles, then
EOT falls. In loopback mode, EOT trips HOLD
which captures the analog sample. Conversion begins on the next rising edge of CLKIN. If operated asynchro-
nously,
EOT will remain low until after HOLD is taken low. When HOLD occurs the analog sample is captured
immediately, but conversion may not begin until four CLKIN cycles later.
EOT will return high
when conversion begins.
2. Timing delay t
d
(relative to CLKIN) can vary between 135 ns to 235 ns over the military temperature range
and over
±
10% supply variation
3.
EOC returns high in 4 CLKIN cycles if A0 = 1 and CS = RD = 0 (Microprocessor Independent Mode);
within 4 CLKIN cycles after a data read (Microprocessor Mode); or 4 CLKIN cycles after
HOLD = 0
is recognized on a rising edge of CLKIN/4.
CS5012A, CS5014, CS5016
DS14F6 2-25
Peaking in the reference’s output impedance can
occur because of capacitive loading at its output.
Any peaking that might occur can be reduced by
placing a small resistor in series with the capaci-
tors (Figure 10). The equation in Figure 10 can
be used to help calculate the optimum value of R
for a particular reference. The term "f
peak
" is the
frequency of the peak in the output impedance of
the reference before the resistor is added.
The CS5012A/14/16 can operate with a wide
range of reference voltages, but signal-to-noise
performance is maximized by using as wide a
signal range as possible. The recommended refer-
ence voltage is between 2.5 and 4.5 V for the
CS5012A and 4.5 V for the CS5014/16. The
CS5012A/14/16 can actually accept reference
voltages up to the positive analog supply. How-
ever, the buffer’s offset may increase as the
reference voltage approaches VA+ thereby in-
creasing external drive requirements at VREF. A
4.5V reference is the maximum reference voltage
recommended. This allows 0.5V headroom for
the internal reference buffer. Also, the buffer en-
lists the aid of an external 0.1
µ
F ceramic
capacitor which must be tied between its output,
REFBUF, and the negative analog supply, VA-. For
more information on references, consult the applica-
tion note: Voltage References for the CS501X Se-
ries of A/D Converters. For an example of using
the CS5012A/14/16 with a 5 volt reference, see
the application note: A Collection of Application
Hints for the CS501X Series of A/D Converters.
Analog Input Connection
The analog input terminal functions similarly to
the VREF input after each conversion when
switching into the track mode. During the first
six CLKIN cycles in the track mode, the buffered
version of the analog input is used for pre-charg-
ing the capacitor array. An additional period is
required for fine-charging directly from AIN to
VREF
REFBUF
VA-
0.1
µ
F
-5V
R
29
28
30
ref
V
C1
1.0
µ
F
0.01
µ
F
C2
+V
ee
CS5012A
CS5014
CS5016
1
R=
2
π
(C
1
+ C
2
) f
peak
Figure 10. Reference Connections
Internal Charge Error (LSB's)
Fine-ChargePre-Charge
Acquisition Time (us)
0.5 1.0 1.5 2.0 2.5
(Delay from EOC)
+12.5
0
-12.5
-25.0
+50
0
-50
-100
+200
0
-200
-400
CS5012ACS5014CS5016
Figure 11. Internal Acquisition Time
CS5012A, CS5014, CS5016
2-26 DS14F6
obtain the specified accuracy. Figure 11 illustrates
this operation. During pre-charge the charge on
the capacitor array first settles to the buffered ver-
sion of the analog input. This voltage is offset
from the actual input voltage. During fine-charge,
the charge then settles to the accurate unbuffered
version.
The acquisition time of the CS5012A/14/16 de-
pends on the CLKIN frequency. This is due to a
fixed pre-charge period. For instance, operating
the CS5012A -12, CS5014 -14 or CS5016 -16
version with an external 4 MHz CLKIN results in
a 3.75
µ
s acquisition time: 1.5
µ
s for pre-charging
(6 clock cycles) and 2.25
µ
s for fine-charging.
Fine-charge settling is specified as a maximum of
2.25
µ
s for an analog source impedance of less
than 200
. (For the CS5012A -7 version it is
specified as 1.32
µ
s.) In addition, the comparator
requires a source impedance of less than 400
around 2 MHz for stability, which is met by prac-
tically all bipolar op amps. Large dc source
impedances can be accommodated by adding ca-
pacitance from AIN to ground (typically 200 pF)
to decrease source impedance at high frequencies.
However, high dc source resistances will increase
the input’s RC time constant and extend the nec-
essary acquisition time. For more information on
input applications, consult the application note:
Input Buffer Amplifiers for the CS501X Family of
A/D Converters.
During the first six clock cycles following a con-
version (pre-charge) in unipolar mode, the
CS5012A is capable of slewing at 20V/
µ
s and the
CS5014/16 can slew at 5V/
µ
s. In bipolar mode,
only half the capacitor array is connected to the
analog input so the CS5012A can slew at 40V/
µ
s,
and the CS5014/16 can slew at 10V/
µ
s. After the
first six CLKIN cycles, the CS5012A will slew at
1.25V/
µ
s in unipolar mode and 3.0V/
µ
s in bipolar
mode, and the CS5014/16 will slew at 0.25V/
µ
s
in unipolar mode and 0.5V/
µ
s in bipolar mode.
Acquisition of fast slewing signals (step func-
tions) can be hastened if the step occurs during or
immediately following the conversion cycle. For
instance, channel selection in multiplexed appli-
cations should occur while the CS5012A/14/16 is
converting (see Figure 12). Multiplexer settling is
thereby removed from the overall throughput
equation, and the CS5012A/14/16 can convert at
full speed.
Convert Channel N+1Convert Channel N
Address N Address N + 1 Address N + 2 Address N + 3
EOC
Output
HOLD
Input
MUX
Address
MUX Settling
to Channel N + 2
Analog
Input
MUX Settling
to Channel N + 1
CS5012A/14/16
CS5012A/14/16
CS5012A/14/16
Figure 12. Pipelined MUX Input Channels
CS5012A, CS5014, CS5016
DS14F6 2-27
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