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CS5014-BP14

Part # CS5014-BP14
Description A/D Converter 16, 14 & 12-BitSelf-Calibrating, 40pin PDip
Category CONVERTER
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

All calibration, conversion, and throughput times
directly scale to CLKIN frequency. Thus,
throughput can be precisely controlled and/or
maximized using an external CLKIN signal. In
contrast, the CS5012A/14/16’s internal oscillator
will vary from unit-to-unit and over temperature.
The CS5012A/14/16 can typically convert with
CLKIN as low as 10 kHz at room temperature.
Initiating Conversions
A falling transition on the HOLD pin places the
input in the hold mode and initiates a conversion
cycle. Upon completion of the conversion cycle,
the CS5012A/14/16 automatically return to the
track mode. In contrast to systems with separate
track-and-holds and A/D converters, a sampling
clock can simply be connected to the HOLD in-
put (Figure 3a). The duty cycle of this clock is
not critical. It need only remain low at least one
CLKIN cycle plus 50 ns, but no longer than the
minimum conversion time or an additional con-
version cycle will be initiated with inadequate
time for acquisition.
Microprocessor-Controlled Operation
Sampling and conversion can be placed under
microprocessor control (Figure 4) by simply gat-
ing the devices’ decoded address with the write
strobe for the HOLD input. Thus, a write cycle to
the CS5012A/14/16’s base address will initiate a
conversion. However, the write cycle must be to
the odd address (A0 high) to avoid initiating a
software controlled reset (see Reset below).
The calibration control inputs, CAL, and
INTRLV are inputs to a set of transparent latches.
These signals are internally latched by CS return-
ing high. They must be in the appropriate state
whenever the chip is selected during a read or
write cycle. Address lines A1 and A2 are shown
connected to CAL and INTRLV in Figure 4 plac-
ing calibration under microprocessor control as
well. Thus, any read or write cycle to the
CS5012A/14/16’s base address will initiate or ter-
minate calibration. Alternatively, A0, INTRLV,
and CAL may be connected to the microproces-
sor data bus.
Conversion Time/Throughput
Upon completing a conversion cycle and return-
ing to the track mode, the CS5012A/14/16
require time to acquire the analog input signal
before another conversion can be initiated. The
acquisition time is specified as six CLKIN cycles
plus 2.25
µ
s (1.32
µ
s for the CS5012A -7 version
only). This adds to the conversion time to define
the converter’s maximum throughput. The con-
version time of the CS5012A/14/16, in turn,
depends on the sampling, calibration, and CLKIN
conditions.
HOLD
CS5012A/14/16
Addr
Dec
A3
AN
Address
Bus
WR
RD
CS
RD
INTRLV
A2
A1
CAL
A0
A0
ADDR VALID
Figure 4b. Conversions under Microprocessor Control
CS5012A/14/16
CS
Addr
Dec
A3
AN
Address
Bus
RDRD
CONCLK HOLD
INTRLV
CAL
A0
A2
A1
A0
ADDR VALID
Figure 4a. Conversions Asynchronous to CLKIN
CS5012A, CS5014, CS5016
DS14F6 2-19
Asynchronous Sampling
The CS5012A/14/16 internally operate from a
clock which is delayed and divided down from
CLKIN (f
CLK
/4). If sampling is not synchronized
to this internal clock, the conversion cycle may
not begin until up to four clock cycles after
HOLD goes low even though the charge is
trapped immediately. In this asynchronous mode
(Figure 3a), the four clock cycles add to the mini-
mum 49, 57 and 65 clock cycles (for the
CS5012A/14/16 respectively) to define the maxi-
mum conversion time (see Figure 5a and
Table 1).
Synchronous Sampling
To achieve maximum throughput, sampling can
be synchronized with the internal conversion
clock by connecting the End-of-Track (EOT) out-
put to HOLD (Figure 3b). The EOT output falls
15 CLKIN cycles after EOC indicating the ana-
log input has been acquired to the
CS5012A/14/16’s specified accuracy. The EOT
output is synchronized to the internal conversion
clock, so the four clock cycle synchronization un-
certainty is removed yielding throughput at
[1/64]f
CLK
for the CS5012A, [1/72]f
CLK
for
CS5014 and [1/80]f
CLK
for CS5016 where f
CLK
is the CLKIN frequency (see Figure 5b and Ta-
ble 1).
*
Conversion
(49 + N cycles)
1 / Throughput
(64 + N cycles)
Output
EOT
Output
EOC
Input
HOLD
Acquisition
(15 cycles)
*Dashed line: CS & RD = 0 CS5012A N = 0
Solid line: See Figure 9 CS5014 N = 8
CS5016 N = 16
Figure 5b. Synchronous (Loopback Mode)
Conversion
Synchronization Uncertainty (4 cycles)
Input
Output
Output
Acquisition
HOLD
EOC
EOT
1 / Throughput
Figure 5a. Asynchronous Sampling (External Clock)
Throughput TimeConversion Time
Sampling Mode
Synchronous (Loopback)
Asynchronous
Min
64 t
clk
N/A
N/A
Max
64 t
clk
59
1.32
µ
s
t
clk
+
59
2.25
µ
s
t
clk
+
Max
+ 235 ns53 t
clk
49 t
clk
+ 235 ns53 t
clk
Min
49 t
clk
49 t
clk
49 t
clk
-7
-12,-24
CS5012A
CS5014
57 t
clk
57 t
clk
+ 235 ns61 t
clk
57 t
clk
72 t
clk
N/A
72 t
clk
67
2.25
µ
s
t
clk
+
Synchronous (Loopback)
Asynchronous
65 t
clk
65 t
clk
+ 235 ns69 t
clk
65 t
clk
80 t
clk
N/A
80 t
clk
75
2.25
µ
s
t
clk
+
Synchronous (Loopback)
Asynchronous
CS5016
Table 1. Conversion and Throughput Times (t
clk
= Master Clock Period)
CS5012A, CS5014, CS5016
2-20 DS14F6
Also, the CS5012A/14/16’s internal RC oscillator
exhibits jitter (typically
±
0.05% of its period),
which is high compared to crystal oscillators. If
the CS5012A/14/16 is configured for synchro-
nous sampling while operating from its internal
oscillator, this jitter will directly affect sampling
purity. The user can obtain best sampling purity
while synchronously sampling by using an exter-
nal crystal-based clock.
Reset
Upon power up, the CS5012A/14/16 must be re-
set to guarantee a consistent starting condition
and initially calibrate the devices. Due to the
CS5012A/14/16’s low power dissipation and low
temperature drift, no warm-up time is required
before reset to accommodate any self-heating ef-
fects. However, the voltage reference input
should have stabilized to within 5%, 1% or
0.25% of its final value, for the CS5012A/14/16
respectively, before RST falls to guarantee an ac-
curate calibration. Later, the CS5012A/14/16 may
be reset at any time to initiate a single full cali-
bration. Reset overrides all other functions. If
reset, the CS5012A/14/16 will clear and initiate a
new calibration cycle mid-conversion or mid-cali-
bration.
Resets can be initiated in hardware or software.
The simplest method of resetting the
CS5012A/14/16 involves strobing the RST pin
high for at least 100 ns. When RST is brought
high all internal logic clears. When it returns low,
a full calibration begins which takes 58,280
CLKIN cycles for the CS5012A (approximately
9.1 ms with a 6.4 MHz clock) and 1,441,020
CLKIN cycles for the CS5016, CS5014 and
CS5012 (approximately 360 ms with a 4 MHz
CLKIN). A simple power-on reset circuit can be
built using a resistor and capacitor, and a
Schmitt-trigger inverter to prevent oscillation (see
Figure 6). The CS5012A/14/16 can also be reset
in software when under microprocessor control.
The CS5012A/14/16 will reset whenever CS, A0,
and HOLD are taken low simultaneously. See the
Microprocessor Interface section (below) to
eliminate the possibility of inadvertent software
reset. The EOC output remains high throughout
the calibration operation and will fall upon its
completion. It can thus be used to generate an
interrupt indicating the CS5012A/14/16 is ready
for operation. While calibrating, the HOLD input
is ignored until EOC falls. After EOC falls, six
CLKIN cycles plus 2.25 µs (1.32 µs for the
CS5012A -7 version only) must be allowed for
signal acquisition before HOLD is activated. Un-
der microprocessor-independent operation (CS,
RD low; A0 high) the CS5014’s and CS5016’s
EOC output will not fall at the completion of the
calibration cycle, but EOT will fall 15 CLKIN
cycles later.
Initiating Calibration
All modes of calibration can be controlled in
hardware or software. Accuracy can thereby be
insured at any time or temperature throughout op-
erating life. After initial calibration at power-up,
the CS5012A/14/16’s charge-redistribution design
yields better temperature drift and more graceful
aging than resistor-based technologies, so calibra-
tion is normally only required once, after
power-up.
The first mode of calibration, reset, results in a
single full calibration cycle. The second type of
calibration, "burst" cal, allows control of partial
calibration cycles. Due to an unforeseen con-
didtion inside the part, asynchronous termination
of calibration may result in a sub-optimal result.
Burst cal should not be used.
C
R
+5V
RST
CS5012A/14/16
Figure 6. Power-on Reset Circuit
CS5012A, CS5014, CS5016
DS14F6 2-21
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