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CS5014-BP14

Part # CS5014-BP14
Description A/D Converter 16, 14 & 12-BitSelf-Calibrating, 40pin PDip
Category CONVERTER
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

VREF – Voltage Reference, PIN 28.
The analog reference voltage which sets the analog input range. It represents positive full scale for
both bipolar and unipolar operation, and its magnitude sets negative full scale in bipolar mode.
Digital Outputs
D0 through D15 – Data Bus Outputs, PINS 2 thru 9, 12 thru 19.
3-state output pins. Enabled by CS and RD, they offer the converter’s output in a format
consistent with the state of BW if A0 is high. If A0 is low, bits D0-D7 offer status register data.
EOT – End Of Track, PIN 37.
If low, indicates that enough time has elapsed since the last conversion for the device to acquire
the analog input signal.
EOC – End Of Conversion, PIN 38.
This output indicates the end of a conversion or calibration cycle. It is high during a conversion
and will fall to a low state upon completion of the conversion cycle indicating valid data is
available at the output. Returns high on the first subsequent read or the start of a new conversion
cycle.
SDATA – Serial Output, PIN 40.
Presents each output data bit after it is determined by the successive approximation algorithm.
Valid on the rising edge of SCLK, data appears MSB first, LSB last, and each bit remains valid
until the next bit appears.
SCLK – Serial Clock Output, PIN 39.
Used to clock converted output data serially from the CS5012A/14/16. Serial data is stable on the
rising edge of SCLK.
Analog Outputs
REFBUF – Reference Buffer Output, PIN 29.
Reference buffer output. A 0.1
µ
F ceramic capacitor must be tied between this pin and VA-.
Miscellaneous
TST – Test, PIN 31.
Allows access to the CS5012A/14/16’s test functions which are reserved for factory use. Must be
tied to DGND.
CS5012A, CS5014, CS5016
DS14F6 2-43
PARAMETER DEFINITIONS
Linearity Error
The deviation of a code from a straight line passing through the endpoints of the transfer
function after zero- and full-scale errors have been accounted for. "Zero-scale" is a point 1/2 LSB
below the first code transition and "full-scale" is a point 1/2 LSB beyond the code transition to
all ones. The deviation is measured from the middle of each particular code. Units in %
Full-Scale.
Differential Linearity
Minimum resolution for which no missing codes is guaranteed. Units in bits.
Full Scale Error
The deviation of the last code transition from the ideal (VREF-3/2 LSB’s).
Units in LSB’s.
Unipolar Offset
The deviation of the first code transition from the ideal (1/2 LSB above AGND) when in
unipolar mode (BP/UP low). Units in LSB’s.
Bipolar Offset
The deviation of the mid-scale transition (011...111 to 100...000) from the ideal (1/2 LSB below
AGND) when in bipolar mode (BP/UP high). Units in LSB’s.
Bipolar Negative Full-Scale Error
The deviation of the first code transition from the ideal when in bipolar mode (BP/UP high). The
ideal is defined as lying on a straight line which passes through the final and mid-scale code
transitions. Units in LSB’s.
Peak Harmonic or Spurious Noise (More accurately, Signal to Peak Harmonic or Spurious Noise)
The ratio of the rms value of the signal to the rms value of the next largest spectral component
below the Nyquist rate (excepting dc). This component is often an aliased harmonic when the
signal frequency is a significant proportion of the sampling rate. Expressed in decibels.
Total Harmonic Distortion
The ratio of the rms sum of all harmonics to the rms value of the signal. Units in percent.
Signal-to-Noise Ratio
The ratio of the rms value of the signal to the rms sum of all other spectral components below
the Nyquist rate (excepting dc), including distortion components. Expressed in decibels.
Aperture Time
The time required after the hold command for the sampling switch to open fully. Effectively a
sampling delay which can be nulled by advancing the sampling signal. Units in nanoseconds.
Aperture Jitter
The range of variation in the aperture time. Effectively the "sampling window" which ultimately
dictates the maximum input signal slew rate acceptable for a given accuracy. Units in
picoseconds.
NOTE: Temperatures specified define ambient conditions in free-air during test and do not refer to the junction
temperature of the device.
CS5012A, CS5014, CS5016
2-44 DS14F6
CS5012A Ordering Guide
Model Throughput Conversion Time Maximum DNL Temp. Range Package
CS5012A-KP12 63 kHz 12.25
µ
s
±
1/2 LSB 0 to 70
°
C 40-Pin Plastic DIP
CS5012A-KP7 100 kHz 7.20
µ
s
±
1/2 LSB 0 to 70
°
C 40-Pin Plastic DIP
CS5012A-KL12 63 kHz 12.25
µ
s
±
1/2 LSB 0 to 70
°
C 44-Pin PLCC
CS5012A-KL7 100 kHz 7.20
µ
s
±
1/2 LSB 0 to 70
°
C 44-Pin PLCC
CS5012A-BP12 63 kHz 12.25
µ
s
±
1/2 LSB -40 to +85
°
C 40-Pin Plastic DIP
CS5012A-BP7 100 kHz 7.20
µ
s
±
1/2 LSB -40 to +85
°
C 40-Pin Plastic DIP
CS5012A-BL12 63 kHz 12.25
µ
s
±
1/2 LSB -40 to +85
°
C 44-Pin PLCC
CS5012A-BL7 100 kHz 7.20
µ
s
±
1/2 LSB -40 to +85
°
C 44-Pin PLCC
5962-8967901QA 63 kHz 12.25
µ
s
±
1/2 LSB -55 to +125
°
C 40-Pin CerDIP
5962-8967901XA 63 kHz 12.25
µ
s
±
1/2 LSB -55 to +125
°
C 44-Pin Ceramic LCC
The CS5012A is recommended for new designs. The following is a list of upgraded part numbers.
Discontinued
Equivalent
Part Number Recommended Device.
CS5012-KP24 CS5012A-KP12
CS5012-KP12 CS5012A-KP12
CS5012-KP7 CS5012A-KP7
CS5012-KL24 CS5012A-KL12
CS5012-KL12 CS5012A-KL12
CS5012-KL7 CS5012A-KL7
CS5012-BD24 CS5012A-BP12
CS5012-BD12 CS5012A-BP12
CS5012-BD7 CS5012A-BP7
CS5012-BL24 CS5012A-BL12
CS5012-BL12 CS5012A-BL12
CS5012-BL7 CS5012A-BL7
CS5012-TD24B 5962-897901QA
CS5012-TD12B 5962-897901QA
CS5012-TE24B 5962-897901XA
CS5012-TE12B 5962-897901XA
CS5012A, CS5014, CS5016
DS14F6 2-45
AS PER EOL MAY 22, 2000
CURRENT PRODUCT REPLACEMENT
BEING OBSOLETED PRODUCT
CS5012A -KP12 40 pin DIP CS5012A -BP7
CS5012A -KP7 40 pin DIP CS5012A -BP7
CS5012A -BP12 40 pin DIP CS5012A -BP7
CS5012A -KL12 44 pin PLCC CS5012A -BL7
CS5012A -KL7 44 pin PLCC CS5012A -BL7
CS5012A -BL12 44 pin PLCC CS5012A -BL7
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