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CS5014-BP14

Part # CS5014-BP14
Description A/D Converter 16, 14 & 12-BitSelf-Calibrating, 40pin PDip
Category CONVERTER
Availability Out of Stock
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1 + $47.15156



Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

HOLD
HOLD SDATA SERIAL OUTPUT
CS5016 (LSB) DATA BUS BIT 0 D0 SCLK SERIAL CLOCK
DATA BUS BIT 1 D1
EOC END OF CONVERSION
CS5014 (LSB) DATA BUS BIT 2 D2
EOT END OF TRACK
DATA BUS BIT 3 D3 VD- NEGATIVE DIGITAL POWER
CS5012 (LSB) DATA BUS BIT 4 D4 CAL CALIBRATE
DATA BUS BIT 5 D5
INTRLV INTERLEAVE
DATA BUS BIT 6 D6 BW BUS WIDTH SELECT
DATA BUS BIT 7 D7 RST RESET
DIGITAL GROUND DGND TST TEST
POSITIVE DIGITAL POWER VD+ VA- NEGATIVE ANALOG POWER
DATA BUS BIT 8 D8 REFBUF REFERENCE BUFFER OUTPUT
DATA BUS BIT 9 D9 VREF VOLTAGE REFERENCE
DATA BUS BIT 10 D10 AGND ANALOG GROUND
DATA BUS BIT 11 D11 AIN ANALOG INPUT
DATA BUS BIT 12 D12 VA+ POSITIVE ANALOG POWER
DATA BUS BIT 13 D13 BP/
UP BIPOLAR/UNIPOLAR SELECT
DATA BUS BIT 14 D14 A0 READ ADDRESS
(MSB) DATA BUS BIT 15 D15
RD READ
CLOCK INPUT CLKIN
CS CHIP SELECT
HOLD
D0 SDATA
D1 SCLK
D2
EOC
D3
EOT
D4 VD-
D5 CAL
D6
INTRLV
NC BW
D7 RST
DGND TST
VD+ VA-
NC NC
D8 REFBUF
NC VREF
D9 AGND
D10 AIN
D11 VA+
D12 BP/
UP
D13 A0
D14
RD
D15
CS
CLKIN
CS5012A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
CS5012
CS5014
CS5016
top
view
18 20 22 24 26 28
1246404244
12
8
10
14
16
7
9
11
13
15
17 29
31
33
35
37
39
34
30
32
36
38
CS5012A
CS5012
CS5014
CS5016
NOTE: All pin references in this data sheet refer to the 40-pin DIP package numbering.
Use this figure to determine pin numbers for 44-pin package.
CS5012A, CS5014, CS5016
2-40 DS14F6
PIN DESCRIPTIONS
Power Supply Connections
VD+ – Positive Digital Power, PIN 11.
Positive digital power supply. Nominally +5 volts.
VD- – Negative Digital Power, PIN 36.
Negative digital power supply. Nominally -5 volts.
DGND – Digital Ground, PIN 10.
Digital ground.
VA+ – Positive Analog Power, PIN 25.
Positive analog power supply. Nominally +5 volts.
VA- – Negative Analog Power, PIN 30.
Negative analog power supply. Nominally -5 volts.
AGND – Analog Ground, PIN 27.
Analog ground.
Oscillator
CLKIN – Clock Input, PIN 20.
All conversions and calibrations are timed from a master clock which can either be supplied by
driving this pin with an external clock signal, or can be internally generated by tying this pin to
DGND.
Digital Inputs
HOLD – Hold, PIN 1.
A falling transition on this pin sets the CS5012A/14/16 to the hold state and initiates a conversion.
This input must remain low at least one CLKIN cycle plus 50 ns.
CS – Chip Select, PIN 21.
When high, the data bus outputs are held in a high impedance state and the input to CAL and
INTRLV are ignored. A falling transition initiates or terminates burst or interleave calibration
(depending on the status of CAL and INTRLV) and a rising transition latches both the CAL and
INTRLV inputs. If RD is low, the data bus is driven as indicated by BW and A0.
RD – Read, PIN 22.
When RD and CS are both low, data is driven onto the data bus. If either signal is high, the data
bus outputs are held in a high impedance state. The data driven onto the bus is determined by BW
and A0.
CS5012A, CS5014, CS5016
DS14F6 2-41
A0 – Read Address, PIN 23.
Determines whether data or status information is placed onto the data bus. When high during the
read operation, converted data is placed onto the data bus; when low, the status register is driven
onto the bus.
BP/UP – Bipolar/Unipolar Input Select, PIN 24.
When high, the device is configured with a bipolar transfer function ranging from -VREF to
+VREF. Encoding is in an offset binary format, with the mid-scale code 100...0000 centered at
AGND. When low, the device is configured for a unipolar transfer function from AGND to VREF.
Unipolar encoding is in straight binary format. Once calibration has been performed, either bipolar
or unipolar mode may be selected without the need to recalibrate.
RST – Reset, PIN 32.
When taken high for at least 100 ns, all internal digital logic is reset. Upon being taken low, a full
calibration sequence is initiated.
BW – Bus Width Select, PIN 33.
When hard-wired high, all 12 data bits are driven onto the bus simultaneously during a data read
cycle. When low, the bus is in a byte wide format. On the first read following a conversion, the
eight MSB’s are driven onto D0-D7. A second read cycle places the four LSB’s with four trailing
zeros on D0-D7. Subsequent reads will toggle the higher/lower order byte. Regardless of BW’s
status, a read cycle with A0 low yields the status information on D0-D7.
INTRLV – Interleave, PIN 34.
When latched low using CS, the device goes into interleave calibration mode. A full calibration
will complete every 2,014 conversions in the CS5012A, and every 72,051 conversions in the
CS5014/16. The effective conversion time extends by 20 clock cycles.
CAL – Calibrate, PIN 35. (See Addendum appending this data sheet))
When latched high using CS, burst calibration results. The device cannot perform conversions
during the calibration period which will terminate only once CAL is latched low again.
Calibration picks up where the previous calibration left off, and calibration cycles complete every
58,280 CLKIN cycles in the CS5012A, and every 1,441,020 CLKIN cycles in the CS5014/16 . If
the device is converting when a calibration is signaled, it will wait until that conversion completes
before beginning.
Analog Inputs
AIN – Analog Input, PIN 26.
Input range in the unipolar mode is zero volts to VREF. Input range in bipolar mode is -VREF to
+VREF. The output impedance of buffer driving this input should be less than or equal to 200 .
CS5012A, CS5014, CS5016
2-42 DS14F6
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