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87666-2

Part # 87666-2
Description CONN CONT RCP 1 POS CRMP ST CBL MNT STRP - Tape and Reel
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

LC876694B/78B/62B
No.6843-13/23
3. Electrical Characteristics at Ta=-30
°
C to +70
°
C, VSS1=VSS2=0V
Ratings
Parameter Symbol Pins Conditions
VDD[V] min. typ. max.
unit
IIH(1) Ports 0,3: N-ch open
drain output
•Output disabled
•VIN=13.5V
(including OFF state leak
current of the output Tr.)
4.5 to 6.0 5
IIH(2) Port 0,1,3,7,8
•Output disabled
•Pull-up resister OFF.
•VIN=VDD
(including OFF state leak
current of the output Tr.)
4.5 to 6.0 1
IIH(3) S16 to S51 without
pull-down resister
(Port C,D,E,F,G)
When configured as an input
port
VIN=VDD
4.5 to 6.0 60
IIH(4)
RES
VIN=VDD 4.5 to 6.0 1
IIH(5) XT1,XT2 When configured as an input
port
VIN=VDD
4.5 to 6.0 1
IIH(6) CF1 VIN=VDD 4.5 to 6.0 15
Input high
current
IIH(7) P87/AN7/MICIN
weak signal input
VIN=VBIS+0.5V
(VBIS : Bias voltage)
4.5 to 6.0 4.2 8.5 15
IIL(1) Port 0,1,3,7,8 •Output disabled
•VIN=VSS
(including OFF state leak
current of the output Tr.)
4.5 to 6.0 -1
IIL(2)
RES
VIN=VSS 4.5 to 6.0 -1
IIL(3) XT1,XT2 When configured as an input
port
VIN=VSS
4.5 to 6.0 -1
IIL(4) CF1 VIN=VSS 4.5 to 6.0 -15
Input low
current
IIL(5) P87/AN7/MICIN
weak signal input
VIN=VBIS-0.5V
(VBIS : Bias voltage)
4.5 to 6.0 -15 -8.5 -4.2
µ
A
VOH(1) IOH=-1.0mA 4.5 to 6.0 VDD-1
VOH(2)
Port 0,1,3: CMOS
output option
IOH=-0.1mA 4.5 to 6.0 VDD-0.5
VOH(3) Port 7 IOH=-0.4mA 4.5 to 6.0 VDD-1
VOH(4) IOH=-20.0mA 4.5 to 6.0 VDD-1.8
VOH(5)
S0/T0–S15/T15
IOH=-1.0mA
IOH at any single pin is not
over 1mA.
4.5 to 6.0 VDD-1
VOH(6) IOH=-5.0mA 4.5 to 6.0 VDD-1.8
Output high
voltage
VOH(7)
S2+ to S51
IOH=-1.0mA
IOH at any single pin is not
over 1mA.
4.5 to 6.0 VDD-1
VOL(1) Port 02, 03 IOL=30mA 4.5 to 6.0 1.5
VOL(2) IOL=10mA 4.5 to 6.0 1.5
Output low
voltage
VOL(3)
Port 0,1,3
IOL=1.6mA 4.5 to 6.0 0.4
V
Pull-up
resistor
Rpu Port 0,1,3,7 VOH=0.9VDD 4.5 to 6.0 15 40 70
k
Continued
LC876694B/78B/62B
No.6843-14/23
Ratings
Parameter Symbol Pins Conditions
VDD[V] min. typ. Max.
unit
IOFF(1) Output P-ch Tr. OFF
•VOUT=VSS
4.5 to 6.0 -1 Output off-
leak current
IOFF(2)
S0/T0 to S15/T15,
S16 to S51 without
pull-down resistor
•Output P-ch Tr. OFF
•VOUT=VDD-40V
4.5 to 6.0 -30
µ
A
Resistance of
the low level
hold Tr.
Rinpd S16 to S51 •Output P-ch Tr. OFF
4.5 to 6.0 200
High voltage
pull-down
resistor
Rpd S0/T0 to S15/T15,
S16 to S51 with
pull-down resistor
•Output P-ch Tr. OFF
•VOUT=3V
•Vp=-30V
5.0 60 100 200
k
VHIS(1) •Port 1,7
RES
4.5 to 6.0 0.1VDD
Hysteresis
voltage
VHIS(2) Port 87 weak signal
input
4.5 to 6.0 0.1VDD
V
Pin
capacitance
CP All pins All other terminals
connected to VSS.
•f=1MHz
•Ta=25
°
C
4.5 to 6.0 10 pF
Input
sensitivity
Vsen Port 87 weak signal
input
4.5 to 6.0 0.12VDD Vpp
LC876694B/78B/62B
No.6843-15/23
4. Serial Input/Output Characteristics at Ta=-30
°
C to +70
°
C, VSS1=VSS2=0V
Ratings
Parameter Symbol Pins Conditions
VDD[V] min. typ. max.
unit
Cycle Time
tSCK(1) 4/3
tSCKL(1)
2/3 Low Level
pulse width
tSCKLA(1)
2/3
tSCKH(1)
2/3 High Level
pulse width
tSCKHA(1)
SCK0(P12) Refer to figure 6 4.5 to 6.0
3
Cycle Time
tSCK(2)
2
Low Level
pulse width
tSCKL(2)
1
Input clock
High Level
pulse width
tSCKH(2)
SCK1(P15) Refer to figure 6 4.5 to 6.0
1
Cycle Time
tSCK(3)
4/3
t
CYC
tSCKL(3)
1/2
Low Level
pulse width
tSCKLA(2)
3/4
tSCKH(3)
1/2 High Level
pulse width
tSCKHA(2)
SCK0(P12) •CMOS output option
•Refer to figure 6
4.5 to 6.0
2
tSCK
Cycle Time
tSCK(4)
2 tCYC
Low Level
pulse width
tSCKL(4)
1/2
Serial clock
Output clock
High Level
pulse width
tSCKH(4)
SCK1(P15) •CMOS output option
•Refer to figure 6
4.5 to 6.0
1/2
tSCK
Data set-up time
t
sDI
0.03
Serial input
Data hold time
t
hDI
SI0(P10),
SI1(P13),
SB0(P11),
SB1(P14)
•Measured with respect
to SI0CLK leading
edge.
•Refer to figure 6
4.5 to 6.0
0.03
Serial output
Output delay
time
tdDO SO0(P12),
SO1(P15),
SB0(011),
SB1(P14)
•Measured with respect
to SI0CLK trailing
edge.
•When port is open
drain: Time delay
from SI0CLK trailing
edge to the SO data
change.
•Refer to figure 6
4.5 to 6.0
1/3
tCYC
+0.05
µ
s
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