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55416-1

Part # 55416-1
Description
Category CONNECTOR
Availability In Stock
Qty 2
Manufacturer Available Qty
AMP
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

TC554161AFT-70,-85,-10,-70L,-85L,-10L
2001-08-17 4/10
OPERATING MODE
MODE CE OE R/W LB UB I/O1~I/O8 I/O9~I/O16 POWER
L L Output Output I
DDO
H L High-Z Output I
DDO
Read L L H
L H Output High-Z I
DDO
L L Input Input I
DDO
H L High-Z Input I
DDO
Write L * L
L H Input High-Z I
DDO
L H H * *
Output Deselect
L
* * H H
High-Z High-Z I
DDO
Standby H * * * * High-Z High-Z I
DDS
* = don't care
H = logic high
L = logic low
TC554161AFT-70,-85,-10,-70L,-85L,-10L
2001-08-17 5/10
AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta =
==
= 0° to 70°C, V
DD
=
==
= 5 V ±
±±
± 10%)
READ CYCLE
TC554161AFT
-70,-70L -85,-85L -10,-10L
SYMBOL PARAMETER
MIN MAX MIN MAX MIN MAX
UNIT
t
RC
Read Cycle Time 70 ¾ 85 ¾ 100 ¾
t
ACC
Address Access Time ¾ 70 ¾ 85 ¾ 100
t
CO
Chip Enable Access Time ¾ 70 ¾ 85 ¾ 100
t
OE
Output Enable Access Time ¾ 35 ¾ 45 ¾ 50
t
BA
Data Byte Control Access Time ¾ 35 ¾ 45 ¾ 50
t
OH
Output Data Hold Time 10 ¾ 10 ¾ 10 ¾
t
COE
Chip Enable Low to Output Active 10 ¾ 10 ¾ 10 ¾
t
OEE
Output Enable Low to Output Active 5 ¾ 5 ¾ 5 ¾
t
BE
Data Byte Control Low to Output Active 5 ¾ 5 ¾ 5 ¾
t
OD
Chip Enable High to Output High-Z ¾ 25 ¾ 30 ¾ 35
t
ODO
Output Enable High to Output High-Z ¾ 25 ¾ 30 ¾ 35
t
BD
Data Byte Control High to Output High-Z ¾ 25 ¾ 30 ¾ 35
ns
WRITE CYCLE
TC554161AFT
-70,-70L -85,-85L -10,-10L
SYMBOL PARAMETER
MIN MAX MIN MAX MIN MAX
UNIT
t
WC
Write Cycle Time 70 ¾ 85 ¾ 100 ¾
t
WP
Write Pulse Width 50 ¾ 55 ¾ 60 ¾
t
CW
Chip Enable to End of Write 60 ¾ 70 ¾ 80 ¾
t
BW
Data Byte Control to End of Write 50 ¾ 55 ¾ 60 ¾
t
AS
Address Setup Time 0 ¾ 0 ¾ 0 ¾
t
WR
Write Recovery Time 0 ¾ 0 ¾ 0 ¾
t
DS
Data Setup Time 30 ¾ 35 ¾ 40 ¾
t
DH
Data Hold Time 0 ¾ 0 ¾ 0 ¾
t
OEW
R/W High to Output Active 5 ¾ 5 ¾ 5 ¾
t
ODW
R/W Low to Output High-Z ¾ 25 ¾ 30 ¾ 35
ns
AC TEST CONDITIONS
PARAMETER TEST CONDITION
Output load 100 pF + 1 TTL Gate
Input pulse level 0.6 V, 2.4 V
Timing measurements 1.5 V
Reference level 1.5 V
t
R
, t
F
5 ns
TC554161AFT-70,-85,-10,-70L,-85L,-10L
2001-08-17 6/10
TIMING DIAGRANS
READ CYCLE
(See Note 1)
WRITE CYCLE 1 (R/W CONTROLLED)
(See Note 4)
Address
R/W
UB , LB
D
OUT
t
AS
t
BW
t
WR
VALID DATA IN
t
ODW
D
IN
t
WP
t
DS
t
DH
t
OEW
(See Note 3)(See Note 2) Hi-Z
t
CW
CE
t
WC
(See Note 5)(See Note 5)
Address
OE
D
OUT
t
RC
t
ACC
t
OD
t
OH
VALID DATA OUT
t
OE
t
BE
t
OEE
t
BD
Hi-Z
Hi-Z
t
CO
CE
UB , LB
t
ODO
t
BA
t
COE
INDETERMINATE
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