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55416-1

Part # 55416-1
Description
Category CONNECTOR
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

TC554161AFT-70,-85,-10,-70L,-85L,-10L
2001-08-17 1/10
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
262,144-WORD BY 16-BIT STATIC RAM
DESCRIPTION
The TC554161AFT is a 4,194,304-bit static random access memory (SRAM) organized as 262,144 words by 16bits.
Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 5V ± 10%
power supply. Advanced circuit technology provides both high speed and low power at an operating current of 10
mA/MHz (typ) and a minimum cycle time of 70 ns. It is automatically placed in low-power mode at 2 mA standby
current (typ) when chip enable ( CE ) is asserted high. There are two control inputs. CE is used to select the device
and for data retention control, and output enable (
OE ) provides fast memory access. Data byte control pin ( LB ,
UB ) provides lower and upper byte access. This device is well suited to various microprocessor system applications
where high speed, low power and battery backup are required. The TC554161AFT is available in a plastic 54-pin
thin-small-outline package (TSOP).
FEATURES
· Low-power dissipation
Operating: 55 mW/MHz (typical)
· Single power supply voltage of 5 V ± 10%
· Power down features using
CE .
· Data retention supply voltage of 2 to 5.5 V
· Direct TTL compatibility for all inputs and outputs
· Standby Current (maximum):
TC554161AFT
-70,-85,-10 -70L,-85L,-10L
5.5 V 100 mA 50 mA
3.0 V 50 mA 25 mA
PIN ASSIGNMENT
(TOP VIEW)
PIN NAMES
A0~A17 Address Inputs
I/O1~I/O16 Data Inputs/Outputs
CE Chip Enable
R/W Read/Write Control
OE Output Enable
LB , UB Data Byte Control
V
DD
Power (+5 V)
GND Ground
NC No Connection
OP* Option
*: OP pin must be open of connected to GND.
· Access Times (maximum):
TC554161AFT
-70,-70L -85,-85L -10,-10L
Access Time 70 ns 85 ns 100 ns
CE Access Time 70 ns 85 ns 100 ns
OE Access Time 35 ns 45 ns 50 ns
· Package:
TSOP II54-P-400-0.80 (AFT) (Weight: 0.57 g typ)
NC
A3
A2
A1
A0
I/O16
I/O15
V
DD
GND
I/O14
I/O13
OP
R/W
I/O12
I/O11
GND
V
DD
I/O10
I/O9
NC
A17
A16
A15
A14
A13
A
4
A
5
A
6
A
7
NC
I/O1
I/O2
V
DD
GND
I/O3
I/O4
OP
NC
I/O5
I/O6
GND
V
DD
I/O7
I/O8
A
8
A
9
A
10
A
11
A
12
NC
1 54
2 53
3 52
4 51
5 50
6 49
7 48
8 47
9 46
10 45
11 44
12 43
13 42
14 41
15 40
16 39
17 38
18 37
19 36
20 35
21 34
22 33
23 32
24 31
25 30
26 29
27 28
CE OE
UB
LB
(Normal pinout)
TC554161AFT-70,-85,-10,-70L,-85L,-10L
2001-08-17 2/10
BLOCK DIAGRAM
MAXIMUM RATINGS
SYMBOL RATING VALUE UNIT
V
DD
Power Supply Voltage -0.3~7.0 V
V
IN
Input Voltage -0.3*~7.0 V
V
I/O
Input/Output Voltage -0.5~V
DD
+ 0.5 V
P
D
Power Dissipation 0.6 W
T
solder
Soldering Temperature (10s) 260 °C
T
stg
Storage Temperature -55~150 °C
T
opr
Operating Temperature 0~70 °C
*: -3.0 V when measured at a pulse width of 30ns
I/O1
CE
V
DD
GND
I/O8
CE
CLOCK
GENERATOR
CE
I/O9
I/O16
OE
LB
CE
A5 A6 A7 A8 A9A10
DATA
OUTPUT
BUFFER
DATA
OUTPUT
BUFFER
DATA
INPUT
BUFFER
DATA
INPUT
BUFFER
A4
A2
A3
A11
A12
A13
A14
A15
A16
A17
A1
UB
R/W
MEMORY CELL ARRAY
2,048
´ 128 ´ 16
(4,194,304)
COLUMN ADDRESS
DECODER
SENSE AMP
COLUMN ADDERSS
REGISTER
COLUMN ADDRESS
BUFFER
ROW ADDRESS
DECODER
ROW ADDRESS
BUFFER
ROW ADDRESS
REGISTER
A0
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
TC554161AFT-70,-85,-10,-70L,-85L,-10L
2001-08-17 3/10
DC RECOMMENDED OPERATING CONDITIONS
(Ta =
==
= 0° to 70°C)
SYMBOL PARAMETER
MIN TYP MAX UNIT
V
DD
Power Supply Voltage 4.5 5.0 5.5 V
V
IH
Input High Voltage 2.2 ¾ V
DD
+ 0.3 V
V
IL
Input Low Voltage -0.3* ¾ 0.8 V
V
DH
Data Retention Supply Voltage 2.0 ¾ 5.5 V
*: -3.0 V when measured at a pulse width of 30 ns
DC CHARACTERISTICS
(Ta =
==
= 0° to 70°C, V
DD
=
==
= 5 V ±
±±
± 10%)
SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT
I
IL
Input Leakage
Current
V
IN
= 0 V~V
DD
¾ ¾ ±1.0 mA
I
LO
Output Leakage
Current
CE = V
IH
or R/W = V
IL
or OE = V
IH
, V
OUT
= 0 V~V
DD
¾ ¾ ±1.0 mA
I
OH
Output High Current V
OH
= 2.4 V -1.0 ¾ ¾ mA
I
OL
Output Low Current V
OL
= 0.4 V 2.1 ¾ ¾ mA
t
cycle
= 70 ns ¾ ¾ 110
t
cycle
= 85 ns, 100 ns ¾ ¾ 100
I
DDO1
CE = V
IL
and R/W = V
IH
,
I
OUT
= 0 mA,
Other Input
= V
IH
/V
IL
t
cycle
= 1 ms ¾ 15 ¾
mA
t
cycle
= 70 ns ¾ ¾ 100
t
cycle
= 85 ns, 100 ns ¾ ¾ 90
I
DDO2
Operating Current
CE = 0.2 V and R/W = V
DD
- 0.2 V,
I
OUT
= 0 mA,
Other Input
= V
DD
- 0.2 V/0.2 V
t
cycle
= 1 ms ¾ 10 ¾
mA
I
DDS1
CE = V
IH
¾ ¾ 3 mA
Ta = 25°C ¾ 2 ¾
-70,-85,-10
Ta
= 0~70°C ¾ ¾ 100
Ta = 25°C ¾ 2 5
I
DDS2
Standby Current
CE = V
DD
- 0.2 V,
V
DD
= 2.0 V~5.5 V
-70L,-85L,-10L
Ta
= 0~70°C ¾ ¾ 50
mA
CAPACITANCE
(Ta =
==
= 25°C, f =
==
= 1 MHz)
SYMBOL PARAMETER TEST CONDITION MAX UNIT
C
IN
Input Capacitance V
IN
= GND 10 pF
C
OUT
Output Capacitance V
OUT
= GND 10 pF
Note: This parameter is periodically sampled and is not 100% tested.
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