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ADS1299EEG-FE Daughter Card Hardware Introduction

By this time the ADS1299EEG FE software will have prompted the user an with error message. Click ‘OK’.

It may be necessary to close the program, power cycle the ADS1299EEG FE and restart the program.

This process may need to be done again should you plug the ADS1299ECG FE into a different USB port

on your computer.

4 ADS1299EEG-FE Daughter Card Hardware Introduction

CAUTION

Many of the components on the ADS1299EEG-FE are susceptible to damage

by electrostatic discharge (ESD). Customers are advised to observe proper

ESD handling procedures when unpacking and handling the EVM, including the

use of a grounded wrist strap, bootstraps, or mats at an approved ESD

workstation. An electrostatic smock and safety glasses should also be worn.

The ADS1299 ECG front-end evaluation board is configured to be used with the TI MMB0 data converter

evaluation platform. The key features of the ADS1299 system on a chip (SOC) are:

• Eight integrated INAs and eight 24-bit high-resolution ADCs

• Low channel noise of 1uVpp for 65Hz bandwidth

• Low power consumption (5mW/channel)

• Data rates of 250SPS to 16kSPS

• 5V unipolar or bipolar analog supply, 1.8V to 3.6V digital supply.

• DC /AC Lead off detection

• On-chip oscillator

• On-chip bias amplifier

• Versatile MUX to enable programmable reference and bias electrode

• SPI data interface

The ADS1299EEG-FE can be used to evaluate the performance of ADS1299 chip. Users can provide any

type of signal directly to the ADS1299 through a variety of hardware jumper settings (J6, JP25). External

support circuits are provided for testing purposes such as external references, clocks, lead-off resistors,

and shield drive amplifiers.

Figure 13 shows the functional block diagram with important jumper names for the EVM.

SLAU443–May 2012 EEG Front-End Performance Demonstration Kit

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ADS1299EEG-FE Daughter Card Hardware Introduction

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Figure 13. ADS1299 EEG-FE Front End Block Diagram

The ADS1299EEG-FE board is a four-layer circuit board. The board layout is provided in Section 9; the

schematics are appended to this document. The following sections explain some of the hardware settings

possible with the EVM for evaluating the ADS1299 under various test conditions.

4.1 Power Supply

The EEG front-end EVM mounts on the MMB0 EVM with connectors J2, J3 and J4. The main power

supplies (+5V, +3V and +1.8V) for the front-end board are supplied by the host board (MMB0) through

connector J4. All other power supplies needed for the front-end board are generated on board by power

management devices. The EVM is shipped in +5V unipolar supply configuration.

The ADS1299 can operate from +5.0V analog supply (AVDD/AVSS) and +1.8V to +3.0V digital supply

(DVDD). A bipolar analog supply (±2.5V) can be used as well. The analog power consumption of the front-

end board can be measured by the current flowing through the JP2 jumper and JP20 jumper. The

ADS1299 can be powered down by shorting jumper JP5.

Test points TP5, TP6, TP7, TP8, TP9, TP10, and TP14 are provided to verify that the host power supplies

are correct. The corresponding voltages are shown in Table 2.

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ADS1299EEG-FE Daughter Card Hardware Introduction

Table 2. Power Supply Test Points

Test Point Voltage

TP7 +5.0V

TP9 +1.8V

TP10 +3.3V

TP5 +5.0V

TP13 +2.5V

TP6 –2.5V

TP8 GND

The front-end board must be properly configured in order to achieve the various power-supply schemes.

The default power-supply setting for the ADS1299EEG-FE is a unipolar analog supply of 5V and DVDD of

either +3V or +1.8V. Table 3 shows the board and component configurations for each analog power-

supply scheme; Table 4 shows the board configurations for the digital supply.

Table 3. Analog Supply Configurations

Unipolar Analog Supply Bipolar Analog Supply

Power Supplies

5V ±2.5V

JP2 (AVDD) 2-3 (default) 1-2

JP20 (AVSS) 1-2 (default) 2-3

U8 Don’t Care TPS72325

U9 Don’t Care TPS73225

Table 4. Digital Supply Configurations

DVDD +3.0V +1.8V

JP24 2-3 (default) 1-2

4.2 Clock

The ADS1299 has an on-chip oscillator circuit that generates a 2.048MHz clock (nominal). This clock can

vary by ±5% over temperature. For applications that require higher accuracy, the ADS1299 can also

accept an external clock signal. The ADS1299EEG-FE provides an option to test both internal and

external clock configurations. It also provides an option to generate the external clock from either the

onboard oscillator or from an external clock source.

The onboard oscillator is powered by the DVDD supply of the ADS1299. Care must be taken to ensure

that the external oscillator can operate either with +1.8V or +3.0V, depending on the DVDD supply

configuration. Table 5 shows the jumper settings for the three options for the ADS1299 clocks.

Table 5. Clock Jumper Options

ADS1299 Clock Internal Clock from the ADS1299 Clock from Oscillator on the EVM External Clock Source

JP18 Not Installed 2-3 (default) 1-2

JP19 Don’t Care 1-2 Don’t Care

J3– pin 17 Don’t Care Don’t Care External Clock Source

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Part #	142-0701-201
Description	SMA COAXIAL CONNECTOR
Category	CONNECTOR
Availability	In Stock
Qty	3

Manufacturer	Available	Qty
Military Spec	Freelance Stock: 2 Ships Immediately
Military Spec	Freelance Stock: 1 Ships Immediately

142-0701-201

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