VCC_5v
DVDD
TP8
TP10
TP9
TP7
C70
0.1uF
C69
0.1uF
C71
100uF
C68
100uF
CLKSEL
SPI_DRDY
SPI_OUT
GPIO2
SPI_CLK
SPI_CS
SPI_START
SPI_IN
GPIO1
Dummy Connector
JP4
/RESET
JP24
JP21
JP22
NOTE: Populate J2, J3, and J4 female connectors from the bottom
EXT_CLK
R67
10K
JP23
DVDD
AGND
AGND
AGND
VCC_1.8V
VCC_3.3V
R74
0
A0
1
A1
2
GND
4
SDA
5
SCL
6
WP
7
VCC
8
A2
3
U10
24AA256-I/ST
C94
0.1uF
VCC_3.3V
R68
NI
VCC_3.3V
R69
NI
R70
NI
R71
0
R72
0
R73
0
SCL
SDA
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
J2
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
J3
12
34
56
78
910
J4
R51
NI
VREFP
R50 NI
C40 NI
3
2
6
7
4
8
U5
NI
AVDD
AVSS
R47
NI
C38
NI
C39
NI
R48
NI
C42 NI
C41 NI
R49
NI
JP3
NI
VIN
2
GND
4
OUT
6
TRIM
5
TEMP
3
N/C
1
N/C
7
N/C
8
U3
NI
C34
NI
AVDD
AVSS
C43
NI
C35
NI
AVSS
AGND
AGND
www.ti.com
Bill of Materials, Layouts and Schematics
Figure 62. External Reference Drivers (Not Installed)
Figure 63. ECG MDK Board Interface Adapter
9.2 Printed Circuit Board Layout
Figure 64 through Figure 69 show the ADS1299EEG-FE PCB layout.
53
SLAU443–May 2012 EEG Front-End Performance Demonstration Kit
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
