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142-0701-201

Part # 142-0701-201
Description SMA COAXIAL CONNECTOR
Category CONNECTOR
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

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Test Options on the EVM
8.5 Internally Generated Test Signal and Other Multiplexer Inputs
ADS1299 internally generates a test signal that can be used for signal integrity check. Also the multiplexer
provides options to measure supply voltage, temperature, etc. Details of these inputs can be found in
Section 5.3.
8.6 Arbitrary Input Signal
Any input signal can be fed to the device on connector J6 as described in Section 4.6. Figure 58 shows
the results obtained when a single ended sinusoidal signal is applied to AIN1 by following the steps
described in Section 4.6.2.
Figure 58. Scope Tab with Sinusoidal Inputs on AIN1
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GPIO1
/RESET
/PWDN
SRB1
SRB2
C4
1uF
C9
100uF
C10
10uF
C1
1uF
C2
1uF
C3
1uF
C20
0.01uF
R3
0
VCAP4
VBG
VCAP2
C13
0.1uF
C14
0.1uF
C12
0.1uF
C5
1uF
C8
NI
C16
0.1uF
C6
1uF
C15
NI
C7
NI
C19
NI
VREFP
BIASINV
BIASOUT
BIASIN
C33
NI
VDD
4
GND
2
Output
3
E/D
1
OSC1
HC735-2.048MHZ
AVDD
AVDDAVDD
AVSS
AVSS
AVSS
BIAS_DRV
VREFP
AVSS
AVSS
AVSS
AVDD
AVDD
DVDD
C11
1uF
DVDD
CLKSEL
SPI_DRDY
SPI_OUT
GPIO2
SPI_CLK
SPI_CS
SPI_START
AVDD
SPI_IN
GPIO1
R6
10K
R7
10K
DVDD
BIAS_DRV
C22 NI
C21 NI
AVSS
AVDD
R4
NI
BIAS_SHD
BIAS_SHD
DVDD
VCAP3
/RESET
/PWDN
SPI_DRDY
GPIO4
SPI_OUT
GPIO2
GPIO3
SPI_CLK
SPI_CS
SPI_START
SPI_IN
CLKSEL
CLK
AVSS
C76
1uF
AVSS AVSS
C77
1uF
AVSS
JP5
C17
1uF
C18
0.1uF
AVDD
1
2
3
4
5
U2
NI
/PWDN
DAISY_IN
GPIO3
GPIO4
DAISY_IN
GPIO3
GPIO4
DAISY_IN
12
34
56
78
910
J5
NI
JP18
EXT_CLK
EXT_CLK
TP11 TP12TP1 TP2
AGND
AGND
AGND
AGND
AGND
AGND AGND
AGND
AGND
AGND
AGND
AGND
AGND
R8
392K
TP3
IN8N
1
IN8P
2
IN7N
3
IN7P
4
IN6N
5
IN6P
6
IN5N
7
IN5P
8
IN4N
9
IN4P
10
IN3N
11
IN3P
12
IN2N
13
IN2P
14
IN1N
15
IN1P
16
SRB2
18
SRB1
17
VREFP
24
VCAP4
26
AVSS
20
RESV3/NC
29
VREFN
25
RESV2/NC
27
/PWDN
35
VCAP1
28
GPIO1
42
DAISY_IN
41
VCAP2
30
/RESET
36
DGND
33
DIN
34
START
38
CLK
37
/CS
39
SCLK
40
GPIO3
45
GPIO2
44
DOUT
43
GPIO4
46
/DRDY
47
DVDD
48
DGND
51
AVSS
32
DVDD
50
DGND
49
CLKSEL
52
AVSS1
53
AVDD1
54
VCAP3
55
AVDD
59
AVDD
56
AVSS
23
AVSS
57
AVSS
58
AVDD
19
AVDD
21
BIASIN
62
BIASINV
61
BIASOUT
63
RESV1
31
AVDD
22
BIASREF
60
RESERVED
64
U1
ADS1299
C95
0.1uF
R75
10K
DVDD
C97
1uF
C99
1uF
JP7
REF_ELEC
JP6
BIAS_ELEC
R23
2M
R24
2M
AIN8N
AIN8P
AIN7N
AIN7P
AIN6N
AIN6P
AIN5N
AIN5P
AIN4N
AIN4P
AIN3N
AIN3P
AIN2N
AIN2P
AIN1N
AIN1P
C98
NI
R25
0
AVDD
AVSS
BIAS_ELEC
REF_ELEC
R5
NI
R1
NI
R2
NI
AVDD
AVSS
BIASREF
JP19
3
2
6
7
4
8
5
U4
OPA376
3
2
6
7
4
8
5
U11
OPA376
C23
1uF
C24
1uF
AVDD
AVSS
3
2
6
7
4
8
5
U4A
NI
AVDD
AVSS
3
2
6
7
4
8
5
U11A
NI
U11_3
U11_6
U11_6
U11_3
U4_6
U4_3
U4_6
U4_3
JP8
R18
NI
R16
NI
R17
NI
R15
0
R13
0
R14
0
Optional 8-MSOP driver
JP17
JP1
BIAS_ELEC
Bill of Materials, Layouts and Schematics
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9 Bill of Materials, Layouts and Schematics
This section contains the complete bill of materials, printed circuit board (PCB) layouts, and schematic
diagrams for the ADS1299EEG-FE.
NOTE: Board layouts are not to scale. These are intended to show how the board is laid out; do not
use for manufacturing ADS1299EEG-FE PCBs.
9.1 ADS1299EEG-FE Front-End Board Schematics
Figure 59 through Figure 63 shown the schematic diagrams of the ADS1299EEG-FE.
Figure 59. ADS1299EEG-FC Schematic
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REF_ELEC
AIN8N
AIN8P
AIN7N
AIN7P
C80
4.7nF
AIN6N
R80
4.99K
AIN6P
R81
4.99K
AIN5N
AIN5P
AIN4N
AIN4P
AIN3N
AIN3P
AIN2N
AIN2P
AIN1N
AIN1P
C82
4.7nF
R82
4.99K
R83
4.99K
AGND
C83
4.7nF
AGND
C81
4.7nF
C84
4.7nF
R84
4.99K
R85
4.99K
AGND
C85
4.7nF
C86
4.7nF
R86
4.99K
R87
4.99K
AGND
C87
4.7nF
C88
4.7nF
R88
4.99K
R89
4.99K
AGND
C89
4.7nF
C90
4.7nF
R90
4.99K
R91
4.99K
AGND
C91
4.7nF
C92
4.7nF
R92
4.99K
R93
4.99K
AGND
C93
4.7nF
C72
4.7nF
R94
4.99K
R95
4.99K
AGND
C73
4.7nF
BIAS_ELEC
BIAS_SHD
AGND
1
2
3
4
5
AIN1
R10
4.99K
R11
4.99K
C75
4.7nF
AGND
R12
4.99K
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
J6
36PIN_IDC
1 2
3 4
5 6
JP25
1) External Input Short to VCM
Jumper on (1-2), (3-4)
2) Ain+ to VCM, VCM drives SRB1
Jumper on (3-4), (5-6)
3) Ain- to VCM and Ain+ to SMA
Jumper on (1-2)
4) Ain+ signal through header, VCM drives SRB1
Jumper on (5-6)
JP81 Setting
VCM: DC Bias from BIAS_ELEC
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Bill of Materials, Layouts and Schematics
Figure 60. ADS1299EEG-FC Jumper Schematic
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