xii

3804 Group (Spec.H)

List of figures

REJ09B0212-0100Z

Rev.1.00 Jan 14, 2005

Fig. 3.5.31 Structure of UART3 control register...................................................................... 3-70

Fig. 3.5.32 Structure of AD/DA control register....................................................................... 3-70

Fig. 3.5.33 Structure of AD conversion register 1 ..................................................................3-71

Fig. 3.5.34 Structure of DAi conversion register (i = 1, 2).................................................... 3-71

Fig. 3.5.35 Structure of AD conversion register 2 ..................................................................3-71

Fig. 3.5.36 Structure of Interrupt source selection register ................................................... 3-72

Fig. 3.5.37 Structure of Interrupt edge selection register ...................................................... 3-73

Fig. 3.5.38 Structure of CPU mode register ............................................................................3-73

Fig. 3.5.39 Structure of Interrupt request register 1 ............................................................... 3-74

Fig. 3.5.40 Structure of Interrupt request register 2 ............................................................... 3-74

Fig. 3.5.41 Structure of Interrupt control register 1 ................................................................ 3-75

Fig. 3.5.42 Structure of Interrupt control register 2 ................................................................ 3-75

Fig. 3.5.43 Structure of Flash memory control register 0 ...................................................... 3-76

Fig. 3.5.44 Structure of Flash memory control register 1 ...................................................... 3-77

Fig. 3.5.45 Structure of Flash memory control register 2 ...................................................... 3-77

Fig. 3.5.46 Structure of Port Pi pull-up control register (i = 0 to 2, 4 to 6)....................... 3-78

Fig. 3.5.47 Structure of Port P3 pull-up control register........................................................ 3-78

Fig. 3.5.48 Structure of I

C slave address register i (i = 0 to 2) ......................................... 3-79

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3804 Group (Spec.H)

List of tables

REJ09B0212-0100Z

Rev.1.00 Jan 14, 2005

List of tables

CHAPTER 1 HARDWARE

Table 1 Support products............................................................................................................ 1-2

Table 2 Pin description................................................................................................................ 1-5

Table 3 Push and pop instructions of accumulator or processor status register ............... 1-9

Table 4 Set and clear instructions of each bit of processor status register ..................... 1-10

Table 5 I/O port function ........................................................................................................... 1-15

Table 6 Interrupt vector addresses and priority..................................................................... 1-24

Table 7 Multi-master I

C-BUS interface functions.................................................................. 1-60

Table 8 Set values of I

C clock control register and SCL frequency................................. 1-62

Table 9 START condition generating timing table................................................................. 1-66

Table 10 STOP condition generating timing table................................................................. 1-66

Table 11 START condition/STOP condition detecting conditions ........................................ 1-67

Table 12 Recommended set value to START/STOP condition set bits (SSC4–SSC0) for each

oscillation frequency .................................................................................................. 1-68

Table 13 Summary of 3804 group (spec. H) ......................................................................... 1-80

Table 14 State of E/W inhibition function ............................................................................... 1-83

Table 15 List of software commands (CPU rewrite mode) .................................................. 1-85

Table 16 Definition of each bit in status register .................................................................. 1-87

Table 17 Description of pin function (Flash Memory Serial I/O Mode 1) .......................... 1-93

Table 18 Description of pin function (Flash Memory Serial I/O Mode 2) .......................... 1-93

Table 19 Interrupt sources, vector addresses and priority.................................................1-101

Table 20 Relative formula for a reference voltage VREF of A/D converter and Vref (at 10-bit A/

D mode) ....................................................................................................................1-103

Table 21 Relative formula for a reference voltage VREF of A/D converter and Vref (at 8-bit A/

D mode) ....................................................................................................................1-103

Table 22

Change of AD conversion register during A/D conversion (at 10-bit A/D mode) .

1-103

Table 23

Change of AD conversion register during A/D conversion (at 8-bit A/D mode) ...

1-104

CHAPTER 2 APPLICATION

Table 2.1.1 Termination of unused pins (in single-chip mode) ............................................... 2-5

Table 2.2.1 Interrupt sources, vector addresses and priority .............................................. 2-12

Table 2.2.2 List of interrupt bits according to interrupt source............................................. 2-17

Table 2.3.1 CNTR0/CNTR1 active edge switch bit function.................................................... 2-25

Table 2.3.2 CNTR2 active edge switch bit function ................................................................ 2-27

Table 2.4.1 Pin function in clock synchronous serial I/O mode............................................2-60

Table 2.4.2 Pin function in UART mode................................................................................... 2-60

Table 2.4.3 Pin function in clock synchronous serial I/O mode............................................2-60

Table 2.4.4

Setting examples of Baud rate generator (BRG) values and transfer bit rate values ...

2-76

Table 2.12.1 State in stop mode .............................................................................................2-149

Table 2.12.2 State in wait mode..............................................................................................2-153

Table 2.13.1 Parallel unit when parallel programming (when using EFP-I provided by Suisei

Electronics System Co., Ltd.)............................................................................2-159

Table 2.13.2 Connection example to programmer when serial programming (4 wires) ..2-159

xiv

3804 Group (Spec.H)

List of tables

REJ09B0212-0100Z

Rev.1.00 Jan 14, 2005

CHAPTER 3 APPENDIX

Table 3.1.1 Absolute maximum ratings....................................................................................... 3-2

Table 3.1.2 Recommended operating conditions (1) ................................................................ 3-3

Table 3.1.3 Recommended operating conditions (2) ................................................................ 3-4

Table 3.1.4 Recommended operating conditions (3) ................................................................3-5

Table 3.1.5 Electrical characteristics (1)..................................................................................... 3-6

Table 3.1.6 Electrical characteristics (2)..................................................................................... 3-7

Table 3.1.7 A/D converter recommended operating conditions............................................... 3-8

Table 3.1.8 A/D converter characteristics................................................................................... 3-8

Table 3.1.9 D/A converter characteristics................................................................................... 3-8

Table 3.1.10 Power source circuit timing characteristics ......................................................... 3-8

Table 3.1.11 Timing requirements (1) ......................................................................................... 3-9

Table 3.1.12 Timing requirements (2) ....................................................................................... 3-10

Table 3.1.13 Switching characteristics ...................................................................................... 3-11

Table 3.1.14 Multi-master I

C-BUS bus line characteristics ..................................................3-14

Table 3.5.1 CNTR0/CNTR1 active edge switch bit function.................................................... 3-65

Table 3.5.2 CNTR2 active edge switch bit function ................................................................ 3-67

Part #	8047F
Description
Category	CONNECTOR
Availability	In Stock
Qty	3

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8047F

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