3804 Group (Spec.H)

List of figures

REJ09B0212-0100Z

Rev.1.00 Jan 14, 2005

Fig. 2.5.11 Structure of Interrupt source selection register ................................................... 2-91

Fig. 2.5.12 Structure of Interrupt request register 1 ............................................................... 2-92

Fig. 2.5.13 Structure of Interrupt request register 2 ............................................................... 2-92

Fig. 2.5.14 Structure of Interrupt control register 1 ................................................................ 2-93

Fig. 2.5.15 Structure of Interrupt control register 2 ................................................................ 2-93

Fig. 2.5.16 I

C-BUS connection structure ................................................................................. 2-94

Fig. 2.5.17 I

C-BUS communication format example .............................................................. 2-95

Fig. 2.5.18 RESTART condition of master reception.............................................................. 2-96

Fig. 2.5.19 SCL waveforms when synchronizing clocks......................................................... 2-97

Fig. 2.5.20 Initial setting example for SMBUS communication..............................................2-99

Fig. 2.5.21 Read Word protocol communication as SMBUS master device .....................2-100

Fig. 2.5.22

Generating of START condition and transmission process of slave address + write bit ...

2-101

Fig. 2.5.23 Transmission process of command .....................................................................2-102

Fig. 2.5.24

Transmission process of RESTART condition and slave address + read bit...

2-103

Fig. 2.5.25 Reception process of lower data .........................................................................2-104

Fig. 2.5.26 Reception process of upper data ........................................................................2-105

Fig. 2.5.27 Generating of STOP condition .............................................................................2-106

Fig. 2.5.28 Communication example as SMBUS slave device............................................2-107

Fig. 2.5.29 Reception process of START condition and slave address ............................2-108

Fig. 2.5.30 Reception process of command...........................................................................2-109

Fig. 2.5.31 Reception process of RESTART condition and slave address .......................2-110

Fig. 2.5.32 Transmission process of lower data....................................................................2-111

Fig. 2.5.33 Transmission process of upper data ...................................................................2-112

Fig. 2.5.34 Reception of STOP condition ...............................................................................2-113

Fig. 2.6.1 Memory map of registers relevant to PWM .........................................................2-118

Fig. 2.6.2 Structure of PWM control register .........................................................................2-118

Fig. 2.6.3 Structure of PWM prescaler ...................................................................................2-119

Fig. 2.6.4 Structure of PWM register ......................................................................................2-119

Fig. 2.6.5 Connection diagram .................................................................................................2-120

Fig. 2.6.6 PWM output timing...................................................................................................2-120

Fig. 2.6.7 Setting of relevant registers ...................................................................................2-121

Fig. 2.6.8 PWM output ..............................................................................................................2-121

Fig. 2.6.9 Control procedure.....................................................................................................2-122

Fig. 2.7.1 Memory map of registers relevant to A/D converter...........................................2-123

Fig. 2.7.2 Structure of AD/DA control register.......................................................................2-123

Fig. 2.7.3 Structure of AD conversion register 1 ..................................................................2-124

Fig. 2.7.4 Structure of AD conversion register 2 ..................................................................2-124

Fig. 2.7.5 Structure of Interrupt source selection register ...................................................2-125

Fig. 2.7.6 Structure of Interrupt request register 2 ...............................................................2-126

Fig. 2.7.7 Structure of Interrupt control register 2 ................................................................2-126

Fig. 2.7.8 Connection diagram .................................................................................................2-127

Fig. 2.7.9 Relevant registers setting .......................................................................................2-127

Fig. 2.7.10 Control procedure (10-bit A/D mode)..................................................................2-128

Fig. 2.7.11 Connection diagram ...............................................................................................2-129

Fig. 2.7.12 Relevant registers setting .....................................................................................2-129

Fig. 2.7.13 Control procedure (8-bit A/D mode) ....................................................................2-130

Fig. 2.8.1 Memory map of registers relevant to D/A converter...........................................2-132

Fig. 2.8.2 Structure of Port P5 direction register ..................................................................2-133

Fig. 2.8.3 Structure of AD/DA control register.......................................................................2-133

Fig. 2.8.4 Structure of DAi converter register........................................................................2-134

Fig. 2.8.5 Peripheral circuit example.......................................................................................2-135

Fig. 2.8.6 Speaker output example .........................................................................................2-135

3804 Group (Spec.H)

List of figures

REJ09B0212-0100Z

Rev.1.00 Jan 14, 2005

CHAPTER 3 APPENDIX

Fig. 3.1.1 Circuit for measuring output switching characteristics (1) ................................... 3-12

Fig. 3.1.2 Circuit for measuring output switching characteristics (2) ................................... 3-12

Fig. 3.1.3 Timing diagram (in single-chip mode) ..................................................................... 3-13

Fig. 3.1.4 Timing diagram of multi-master I

C-BUS ................................................................ 3-14

Fig. 3.2.1 Power source current standard characteristics (in high-speed mode) ............... 3-15

Fig. 3.2.2 Power source current standard characteristics (in middle-speed mode) ........... 3-15

Fig. 3.2.3 Power source current standard characteristics (in low-speed mode) ................. 3-16

Fig. 3.2.4 Power source current standard characteristics (in high-speed mode, f(XIN) = 16.8

MHz, WAIT state) ....................................................................................................... 3-16

Fig. 3.2.5 Power source current standard characteristics (in middle-speed mode, f(XIN) = 16.8

MHz, WAIT state) ....................................................................................................... 3-17

Fig. 3.2.6

Power source current standard characteristics (in low-speed mode, WAIT state)......

3-17

Fig. 3.2.7 Power source current standard characteristics (in high-speed mode, f(XIN) = 16.8

MHz, A/D converter operating) ................................................................................. 3-18

Fig. 3.2.8 Power source current standard characteristics (at oscillation stopping) ............ 3-18

Fig. 3.2.9 CMOS output port P-channel side characteristics (Ta = 25 °C)......................... 3-19

Fig. 3.2.10 CMOS output port N-channel side characteristics (Ta = 25 °C) ......................3-19

Fig. 3.2.11

N-channel open-drain output port N-channel side characteristics (Ta = 25 °C) ....

3-20

Fig. 3.2.12

CMOS large current output port N-channel side characteristics (Ta = 25 °C) ....

3-20

Fig. 3.2.13 CMOS input port at pull-up characteristics (Ta = 25 °C) .................................. 3-21

Fig. 2.8.7 Relevant registers setting .......................................................................................2-136

Fig. 2.8.8 Control procedure.....................................................................................................2-137

Fig. 2.9.1 Memory map of registers relevant to watchdog timer ........................................2-139

Fig. 2.9.2 Structure of Watchdog timer control register .......................................................2-139

Fig. 2.9.3 Structure of CPU mode register ............................................................................2-140

Fig. 2.9.4 Watchdog timer connection and division ratio setting ........................................2-141

Fig. 2.9.5 Relevant registers setting .......................................................................................2-142

Fig. 2.9.6 Control procedure.....................................................................................................2-142

Fig. 2.10.1 Example of poweron reset circuit ........................................................................2-143

Fig. 2.10.2 RAM backup system ..............................................................................................2-143

Fig. 2.11.1 Structure of CPU mode register ..........................................................................2-145

Fig. 2.11.2 Connection diagram ...............................................................................................2-146

Fig. 2.11.3 Status transition diagram during power failure ..................................................2-146

Fig. 2.11.4 Setting of relevant registers .................................................................................2-147

Fig. 2.11.5 Control procedure...................................................................................................2-148

Fig. 2.12.1 Oscillation stabilizing time at restoration by reset input ..................................2-150

Fig. 2.12.2

Execution sequence example at restoration by occurrence of INT

interrupt request...

2-152

Fig. 2.12.3 Reset input time .....................................................................................................2-154

Fig. 2.13.1 Memory map of M38049FFHSP/FP/HP/KP ........................................................2-156

Fig. 2.13.2 Memory map of registers relevant to flash memory .........................................2-157

Fig. 2.13.3 Structure of Flash memory control register 0 ....................................................2-157

Fig. 2.13.4 Structure of Flash memory control register 1 ....................................................2-158

Fig. 2.13.5 Structure of Flash memory control register 2 ....................................................2-158

Fig. 2.13.6 Rewrite example of built-in flash memory in standard serial I/O mode.........2-162

Fig. 2.13.7 Connection example in standard serial I/O mode (1).......................................2-163

Fig. 2.13.8 Connection example in standard serial I/O mode (2).......................................2-163

Fig. 2.13.9 Connection example in standard serial I/O mode (3).......................................2-164

Fig. 2.13.10 Example of rewrite system for built-in flash memory in CPU rewrite mode (single-

chip mode) ............................................................................................................2-165

3804 Group (Spec.H)

List of figures

REJ09B0212-0100Z

Rev.1.00 Jan 14, 2005

Fig. 3.2.14 A/D conversion standard characteristics (f(XIN) = 8 MHz) .................................3-23

Fig. 3.2.15 A/D conversion standard characteristics (f(XIN) = 12 MHz) ............................... 3-24

Fig. 3.2.16 A/D conversion standard characteristics (f(XIN) = 16 MHz) ............................... 3-25

Fig. 3.2.17 D/A conversion standard characteristics............................................................... 3-26

Fig. 3.3.1 Sequence of changing relevant register ................................................................. 3-29

Fig. 3.3.2 Sequence of check of interrupt request bit............................................................ 3-30

Fig. 3.3.3 Sequence of setting serial I/Oi (i = 1, 3) control register again......................... 3-33

Fig. 3.3.4 Ceramic resonator circuit .......................................................................................... 3-38

Fig. 3.3.5 Initialization of processor status register ................................................................ 3-40

Fig. 3.3.6 Sequence of PLP instruction execution .................................................................. 3-41

Fig. 3.3.7 Stack memory contents after PHP instruction execution .....................................3-41

Fig. 3.3.8 Status flag at decimal calculations .......................................................................... 3-41

_____________

Fig. 3.4.1 Wiring for the RESET pin ......................................................................................... 3-43

Fig. 3.4.2 Wiring for clock I/O pins ........................................................................................... 3-44

Fig. 3.4.3 Wiring for CNVSS pin.................................................................................................. 3-44

Fig. 3.4.4 Bypass capacitor across the VSS line and the VCC line ........................................ 3-45

Fig. 3.4.5 Analog signal line and a resistor and a capacitor ................................................ 3-46

Fig. 3.4.6 Wiring for a large current signal line ...................................................................... 3-47

Fig. 3.4.7 Wiring of signal lines where potential levels change frequently ......................... 3-47

Fig. 3.4.8 VSS pattern on the underside of an oscillator ........................................................3-48

Fig. 3.4.9 Setup for I/O ports..................................................................................................... 3-48

Fig. 3.4.10 Watchdog timer by software................................................................................... 3-49

Fig. 3.5.1 Structure of Port Pi.................................................................................................... 3-50

Fig. 3.5.2 Structure of Port Pi direction register ..................................................................... 3-50

Fig. 3.5.3 Structure of Timer 12, X count source selection register .................................... 3-51

Fig. 3.5.4 Structure of Timer Y, Z count source selection register ...................................... 3-52

Fig. 3.5.5 Structure of MISRG ................................................................................................... 3-53

Fig. 3.5.6 Structure of I

C data shift register........................................................................... 3-53

Fig. 3.5.7 Structure of I

C special mode status register ........................................................ 3-54

Fig. 3.5.8 Structure of I

C status register.................................................................................3-55

Fig. 3.5.9 Structure of I

C control register ............................................................................... 3-56

Fig. 3.5.10 Structure of I

C clock control register ................................................................... 3-57

Fig. 3.5.11 Structure of I

C START/STOP condition control register ................................... 3-58

Fig. 3.5.12 Structure of I

C special mode control register..................................................... 3-58

Fig. 3.5.13

Structure of Transmit/Receive buffer register 1, Transmit/Receive buffer register 3 ....

3-59

Fig. 3.5.14 Structure of Serial I/O1 status register, Serial I/O3 status register ................. 3-59

Fig. 3.5.15 Structure of Serial I/O1 control register................................................................3-60

Fig. 3.5.16 Structure of UART1 control register...................................................................... 3-61

Fig. 3.5.17 Structure of Baud rate generator i ........................................................................ 3-61

Fig. 3.5.18 Structure of Serial I/O2 control register................................................................3-62

Fig. 3.5.19 Structure of Watchdog timer control register ....................................................... 3-62

Fig. 3.5.20 Structure of Serial I/O2 register............................................................................. 3-63

Fig. 3.5.21 Structure of Prescaler 12, Prescaler X, Prescaler Y .......................................... 3-63

Fig. 3.5.22 Structure of Timer 1 ................................................................................................ 3-64

Fig. 3.5.23 Structure of Timer 2, Timer X, Timer Y ............................................................... 3-64

Fig. 3.5.24 Structure of Timer XY mode register .................................................................... 3-65

Fig. 3.5.25 Structure of Timer Z low-order, Timer Z high-order ........................................... 3-66

Fig. 3.5.26 Structure of Timer Z mode register....................................................................... 3-66

Fig. 3.5.27 Structure of PWM control register ......................................................................... 3-68

Fig. 3.5.28 Structure of PWM prescaler ................................................................................... 3-68

Fig. 3.5.29 Structure of PWM register ...................................................................................... 3-68

Fig. 3.5.30 Structure of Serial I/O3 control register................................................................3-69

Part #	8047F
Description
Category	CONNECTOR
Availability	In Stock
Qty	3

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3 +	$656.74284

8047F

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