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141050

Part # 141050
Description TYPE I 42VDC 50 AMPAUTO RESET PANEL MOUNT
Category CIRCUIT BREAKER
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Qty 199
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

WMS7140/1
Publication Release Date: April 21, 2005
- 7 - Revision 1.1
7. FUNCTIONAL DESCRIPTION
The WMS7140/1, a nonvolatile digitally programmable potentiometers with 16 taps, with or without
output buffer, is designed to operate as both a potentiometer or a variable resistor depending upon
the output configuration selected.
The chip can store up to one 8-bit word in a nonvolatile memory (NVMEM0) in order to set the tap
register value when the device is powered up.
The WMS7140/1 is controlled by a serial Up-Down (3-wire) interface that allows setting the tap
register value as well as storing data in the nonvolatile memory.
7.1. POTENTIOMETER AND RHEOSTAT MODES
The WMS7140/1 can operate as either a rheostat or as a potentiometer (voltage divider). When in the
potentiometer configuration there are two possible modes. One is done using WMS7140 Winpot
device without the output buffer and the other mode is done with WMS7141 WinPot device with the
output buffer.
7.1.1. Rheostat Configuration
The WMS7140/1 acts as a two terminal resistive element in the rheostat configuration where one
terminal can be connected to either the end point pins of the resistor (V
A
and V
B
) and the other
terminal is the wiper (V
W
) pin. This configuration controls the resistance between the two terminals
and the resistance can be adjusted by sending the corresponding tap register setting to the
WMS7140/1 or can also be set by loading a pre-set tap register value from nonvolatile memory
NVMEM0 upon power up.
7.1.2. Potentiometer Configuration
In potentiometer configuration an input voltage is applied to either one of the end point pins (V
A
or V
B
).
The voltage on the wiper pin will be proportional to the voltage difference between V
A
and V
B
and the
wiper setting. The resistance cannot be directly measured in this configuration.
7.2. NON-VOLATILE MEMORY (NVMEM)
The WMS7140/1 has one NVMEM position available for storing the potentiometer setting. The
NVMEM position can be directly written via the Up/Down interface. The potentiometer is loaded with
the value stored in the NVMEM0 on power up.
WMS7140/1
- 8 -
7.3.
SERIAL DATA INTERFACE
The Up/Down family has a 3-wire Serial Data Interface consisting of CS , INC , U/
D
pins. Only
UP/DOWN operations can be performed. The key features of this interface include:
Increment/Decrement operations on the tap register (TR)
Direct refresh of tap register (TR) from internal NVMEM
Nonvolatile storage of the present tap register value into the NVMEM and automatic recall at
power up
For WMS7141 devices, output buffer amplifier
7.4. OPERATION OVERVIEW
The wiper position or the Tap Register(TR) setting can only be changed by the UP/DOWN operation
with the combination of
CS
, U/D , and
INC
signals. When
CS
is low, the part will be activated and
the TR setting can be changed by toggling
INC , and TR will move up when U/ D is High and move
down when U/
D
is Low. The TR setting will be stored into the user NVMEM automatically each time
CS goes high while INC holds high. Otherwise, if INC is low when CS goes high, the TR setting
will not be stored. The NVMEM content will be automatically loaded into TR at Power On. The user
NVMEM can be tested through the voltage measurement on the wiper pin after saving TR setting into
the NVMEM and reloading into the TR. When the TR setting is already at LOW, further DOWN
operations won’t change the setting. Similarly, when TR setting is at HIGH, further UP operations
won’t change the setting.
When
CS is held HIGH, the part will be in Standby mode and the TR setting will not be changed.
The operating modes of Up/Down are summarized below.
CS
U/
D INC
Operation
Low High High to Low Wiper toward V
A
Low Low High to Low Wiper toward V
B
Low to High x High Store Wiper Position
Low to High x Low No Store, Return to Standby
High x x Standby
Note: x means don’t care
WMS7140/1
Publication Release Date: April 21, 2005
- 9 - Revision 1.1
8. TIMING DIAGRAMS
Conditions: V
DD
= +2.7V to 5.5V, V
A
= V
DD
, V
B
= 0V, T = 25°C
FIGURE 3 –WMS7140/1 TIMING DIAGRAM
Note:
[1] MI in the AC Timing diagram (Figure 3) refers to the minimum incremental change in the wiper output due to a change in the
wiper position.
U
/D
CS
INC
t
I
L
t
DI
t
ID
t
IH
t
C
YC
t
C
I
t
IC
t
F
t
R
V
W
MI
[1]
90%
90%
1
0%
(
store
)
t
CPH
t
I
W
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