- 16 -`

AUGUST08,2012|DATASHEET| Rev3.1

IR3894

12AHighlyIntegratedSupIRBuck

Single‐InputVoltage,SynchronousBuckRegulator

PD‐97745

TYPICALOPERATINGCHARACTERISTICS(‐40°CTO+125°C)



Note:SeeOverCurrentprotectionsectionNote:SeeOverCurrentProtectionsection



- 17 -`

AUGUST08,2012|DATASHEET| Rev3.1

IR3894

12AHighlyIntegratedSupIRBuck

Single‐InputVoltage,SynchronousBuckRegulator

PD‐97745

THEORYOFOPERATION



DESCRIPTION

TheIR3894usesaPWMvoltagemodecontrolschemewith

externalcompensationtoprovidegoodnoiseimmunity

andmaximumflexibilityinselectinginductorvaluesand

capacitortypes.

Theswitchingfrequencyisprogrammablefrom300KHz

to1.5MHzandprovidesthecapabilityofoptimizingthe

designintermsofsizeandperformance.



IR3894providespreciselyregulatedoutputvoltage

programmedviatwoexternalresistorsfrom0.5Vto

0.86*Vin.

TheIR3894operateswithaninternalbiassupply(LDO)

whichisconnectedtotheVcc/LDO_outpin.Thisallows

operationwithsinglesupply.Thebiasvoltageisvariable

accordingtoloadcondition.Iftheoutputload

currentis

lessthanhalfofthepeak‐to‐peakinductorcurrent,alower

biasvoltage,4.4V,isusedastheinternalgatedrive

voltage;otherwise,ahighervoltage,6.4V,isused.

Thisfeaturehelpstheconvertertoreducepowerlosses.

TheICcanalsobeoperatedwithanexternalsupply

from

4.5to7.5V,allowinganextendedoperatinginputvoltage

(PVin)rangefrom1.0Vto21V.ForusingtheinternalLDO

supply,theVinpinshouldbeconnectedtoPVinpin.

Ifanexternalsupplyisused,itshouldbeconnectedto

Vcc/LDO_outpinandtheVinpinshouldbe

shortedto

Vcc/LDO_outpin.

Thedeviceutilizestheon‐resistanceofthelowside

MOSFET(syncFET)fortheovercurrentprotection.This

methodenhancestheconverter’sefficiencyandreduces

costbyeliminatingtheneedforexternalcurrentsense

resistor.

IR3894includestwolowR

ds(on)

MOSFETsusingIR’sHEXFET

technology.Thesearespecificallydesignedforhigh

efficiencyapplications.

UNDER‐VOLTAGELOCKOUTANDPOR

Theunder‐voltagelockoutcircuitmonitorsthevoltageof

Vcc/LdopinandtheEnableinput.Itassuresthatthe

MOSFETdriveroutputsremainintheoffstatewhenever

eitherofthesetwosignalsdropbelowthesetthresholds.

NormaloperationresumesonceVcc/LDO_OutandEnable

riseabovetheirthresholds.

ThePOR

(PowerOnReady)signalisgeneratedwhenall

thesesignalsreachthevalidlogiclevel(seesystemblock

diagram).WhenthePORisassertedthesoftstart

sequencestarts(seesoftstartsection).

ENABLE

TheEnablefeaturesanotherlevelofflexibilityforstartup.

TheEnablehasprecisethresholdwhichisinternally

monitoredbyUnder‐VoltageLockout(UVLO)circuit.

Therefore,theIR3894willturnononlywhenthevoltage

attheEnablepinexceedsthisthreshold,typically,1.2V.

IftheinputtotheEnablepin

isderivedfromthebus

voltagebyasuitablyprogrammedresistivedivider,itcan

beensuredthattheIR3894doesnotturnonuntilthebus

voltagereachesthedesiredlevel(Fig.4).Onlyafterthebus

voltagereachesorexceedsthislevelandvoltageatthe

Enablepinexceeds

itsthreshold,IR3894willbeenabled.

Therefore,inadditiontobeingalogicinputpintoenable

theIR3894,theEnablefeature,withitsprecisethreshold,

alsoallowstheusertoimplementanUnder‐Voltage

Lockoutforthebusvoltage(PVin).Thisisdesirable

particularlyforhighoutputvoltageapplications,where

we

mightwanttheIR3894tobedisabledatleastuntilPVIN

exceedsthedesiredoutputvoltagelevel.

Pvin (12V)

Vcc

Enable

Intl_SS

10. 2 V

Enable Threshold = 1.2V



Figure4:NormalStartup,deviceturnson

whenthebusvoltagereaches10.2V

AresistordividerisusedatENpinfromPVintoturnonthe

deviceat10.2V.



- 18 -`

AUGUST08,2012|DATASHEET| Rev3.1

IR3894

12AHighlyIntegratedSupIRBuck

Single‐InputVoltage,SynchronousBuckRegulator

PD‐97745

Pvin(12V)

Vcc

Intl_SS

Enable >1.2V

Vp>1V



Figure5a:RecommendedstartupforNormaloperation

Pvin (12V)

Vcc

Enable > 1. 2 V

Intl_SS



Figure5b:Recommendedstartupforsequencingoperation

(ratiometricorsimultaneous)

Pvin (12V)

Vcc

Enable > 1. 2 V

Intl_SS

Vref=0



Figure5c:Recommendedstartupfor

memorytrackingoperation(Vtt‐DDR)

Figure5ashowstherecommendedstart‐upsequencefor

thenormal(non‐tracking,non‐sequencing)operationof

IR3894,whenEnableisusedasalogicinput.Figure5b

showstherecommendedstartupsequenceforsequenced

operationofIR3894withEnableusedaslogicinput.Figure

5cshowstherecommendedstartupsequence

fortracking

operationofIR3894withEnableusedaslogicinput.

Innormalandsequencingmodeoperation,Vrefisleft

floating.A1nFceramiccapacitorisrecommended

betweenthispinandGnd.Intrackingmodeoperation,

VrefshouldbetiedtoGnd.

ItisrecommendedtoapplytheEnablesignal

aftertheVCC

voltagehasbeenestablished.IftheEnablesignalispresent

beforeVCC,a50kΩresistorcanbeusedinserieswiththe

EnablepintolimitthecurrentflowingintotheEnablepin.

PRE‐BIASSTARTUP

IR3894isabletostartupintopre‐chargedoutput,which

preventsoscillationanddisturbancesoftheoutput

voltage.

Theoutputstartsinasynchronousfashionandkeepsthe

synchronousMOSFET(SyncFET)offuntilthefirstgate

signalforcontrolMOSFET(CtrlFET)isgenerated.Figure6a

showsatypicalPre

‐Biasconditionatstartup.ThesyncFET

alwaysstartswithanarrowpulsewidth(12.5%ofa

switchingperiod)andgraduallyincreasesitsdutycycle

withastepof12.5%untilitreachesthesteadystatevalue.

Thenumberofthesestartuppulsesforeachstepis16and

it’sinternallyprogrammed.Figure6bshowstheseriesof

16x8startuppulses.

[V]

[Time]

Pre-Bias

Voltage



Figure6a:Pre‐Biasstartup

... ... ...

HDRv

... ... ...

End of

LDRv

12.5% 25%

87.5%

...



Figure6b:Pre‐Biasstartuppulses

Part #	ERJ-3EKF1000V
Description	RES THKFLM 0603 100 OHM 1% 1/10W 100PPM/ C SMD - Cut TR (S
Category	CHIP RESISTOR
Availability	Out of Stock
Qty	0

ERJ-3EKF1000V

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