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C3225X5R0J107M

Part # C3225X5R0J107M
Description Cap Ceramic 100uF 6.3V X5R 20% SMD 1210 85C Plastic T/R
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Data Sheet ADP2164
Rev. 0 | Page 13 of 20
FUNCTIONAL BLOCK DIAGRAM
09944-036
SOFT
START
+
+
+
G
M
Z
COMP
ERROR AMP
LOGIC
CONTROL
0.6V
PFET
NFET
0.66V
0.54V
+
+
PMOS
CURRENT
SENSE AMP
NMOS
CURRENT
SENSE AMP
OSCILLATOR
SLOPE
COMPENSATION
REGULATOR
UVLO
ADP2164
PGND
CLK
RTSYNC
V
IN EN PVIN
SW
GND
PGOOD
FB
TRK
Figure 36. Functional Block Diagram
ADP2164 Data Sheet
Rev. 0 | Page 14 of 20
THEORY OF OPERATION
INTEGRATED SOFT START
The ADP2164 is a step-down dc-to-dc regulator that uses
a fixed-frequency, peak current mode architecture with an
integrated high-side switch and low-side synchronous rectifier.
The high switching frequency and tiny, 16-lead, 4 mm × 4 mm
LFCSP package provide a small, step-down dc-to-dc regulator
solution. The integrated high-side switch (P-channel MOSFET)
and synchronous rectifier (N-channel MOSFET) yield high
efficiency.
The ADP2164 has integrated soft start circuitry to limit the
output voltage rise time and reduce inrush current at startup.
The soft start time is set at 2048 clock cycles.
If the output voltage is precharged before the part is turned
on, the ADP2164 prevents a reverse inductor current—which
would discharge the output capacitor—until the soft start
voltage exceeds the voltage on the FB pin.
The ADP2164 operates with an input voltage from 2.7 V to 6.5 V
and regulates the output voltage down to 0.6 V. The ADP2164 is
also available with preset output voltage options of 3.3 V, 2.5 V,
1.8 V, 1.5 V, 1.2 V, and 1.0 V.
OSCILLATOR AND SYNCHRONIZATION
The ADP2164 switching frequency is controlled by the RT pin.
If the RT pin is connected to GND, the switching frequency is
set to 600 kHz. If the RT pin is connected to VIN, the switching
frequency is set to 1.2 MHz.
CONTROL SCHEME
The ADP2164 uses a fixed-frequency, peak current mode
PWM control architecture. At the start of each oscillator cycle,
the P-channel MOSFET switch is turned on, placing a positive
voltage across the inductor. Current in the inductor increases
until the current sense signal crosses the peak inductor current
level, turns off the P-channel MOSFET switch, and turns on the
N-channel MOSFET synchronous rectifier. This action places a
negative voltage across the inductor, causing the inductor current
to decrease. The synchronous rectifier stays on for the rest of
the cycle.
Connecting a resistor from RT to GND allows programming
of the switching frequency from 500 kHz to 1.4 MHz. Use the
following equation to set the switching frequency:
(kHz)
000,54
)(k
S
f
RT =Ω
Figure 37 shows the typical relationship between the switching
frequency and the RT resistor.
1600
1400
1200
1000
800
600
400
200
20 40 60 80 100 120 140 160 180
RT RESISTOR (k)
FREQUENCY (kHz)
09944-037
The peak inductor current level is set by the compensation
(COMP) voltage. The COMP voltage is the output of a transcon-
ductance error amplifier that compares the feedback voltage
with an internal 0.6 V reference (see Figure 36).
SLOPE COMPENSATION
To prevent subharmonic oscillations, slope compensation
stabilizes the internal current control loop of the ADP2164
when the part operates at or beyond a 50% duty cycle. Slope
compensation is implemented by summing an artificial voltage
ramp with the current sense signal during the on time of the
P-channel MOSFET switch. This voltage ramp depends on the
output voltage. When operating at high output voltages, slope
compensation increases. The slope compensation ramp value
determines the minimum inductor value that can be used to
prevent subharmonic oscillations.
Figure 37. Switching Frequency vs. RT Resistor
To synchronize the ADP2164, drive an external clock at the
SYNC pin. The frequency of the external clock can be in the
range of 500 kHz to 1.4 MHz.
PRECISION ENABLE/SHUTDOWN
The EN pin is a precision analog input that enables the device
when the voltage exceeds 1.2 V (typical); this pin has 100 mV
hysteresis. When the enable voltage falls below 1.1 V (typical),
the part turns off. To force the ADP2164 to start automatically
when input power is applied, connect the EN pin to the VIN pin.
When the SYNC pin is driven by an external clock, the user
can configure the switching frequency to be in phase with the
external clock or 180° out of phase with the external clock, as
follows:
If the RT pin is connected to GND or to a resistor, the
switching frequency is in phase with the external clock.
When the ADP2164 is shut down, the soft start capacitor is
discharged. This causes a new soft start cycle to begin when
the part is reenabled.
If the RT pin is connected to VIN, the switching frequency
is 180° out of phase with the external clock.
An internal pull-down resistor (1 MΩ) prevents accidental
enabling of the part if the EN input is left floating.
Data Sheet ADP2164
Rev. 0 | Page 15 of 20
POWER GOOD
PGOOD is an active high, open-drain output and requires a
resistor to pull it up to the logic supply voltage. PGOOD high
indicates that the voltage on the FB pin (and, therefore, the
output voltage) is within 10% of the desired value. PGOOD low
indicates the opposite. There is a 16-cycle waiting period after
the FB voltage is detected as being out of bounds. If FB returns
to within the ±10% range, it is ignored by the PGOOD circuitry.
CURRENT LIMIT AND SHORT-CIRCUIT PROTECTION
The ADP2164 has a peak current limit protection circuit to
prevent current runaway. The peak current limit is 6.2 A. When
the inductor current reaches the peak current limit, the high-side
MOSFET turns off and the low-side MOSFET turns on until the
next cycle begins.
The overcurrent counter is incremented by 1 at each peak
current limit event. If the overcurrent counter exceeds 10, the
part enters hiccup mode, and the high-side FET and low-side
FET are both turned off. The part remains in this mode for
4096 clock cycles and then attempts to restart using soft start.
If the current limit fault has cleared, the part resumes normal
operation. If the current limit fault has not cleared, the part
reenters hiccup mode after first counting 10 current limit
violations.
OVERVOLTAGE PROTECTION (OVP)
Overvoltage protection (OVP) circuitry is integrated in the
ADP2164. The output voltage is continuously monitored by
a comparator through the FB pin, which is at 0.6 V (typical)
under normal operation. The comparator is activated when the
FB voltage exceeds 0.66 V (typical), thus indicating an output
overvoltage condition. If the voltage remains above the OVP
threshold for 16 clock cycles, the high-side MOSFET turns off
and the low-side MOSFET turns on until the current through it
reaches the −1.3 A current limit. Both MOSFETs remain in the
off state until FB falls below 0.54 V (typical), after which the
part restarts. The behavior of PGOOD under this condition is
described in the Power Good section.
UNDERVOLTAGE LOCKOUT (UVLO)
Undervoltage lockout (UVLO) circuitry is integrated in the
ADP2164. If the input voltage falls below 2.5 V, the ADP2164
shuts down, and both the power switch and the synchronous
rectifier turn off. When the voltage rises above 2.6 V again,
the soft start is initiated, and the part is enabled.
THERMAL SHUTDOWN
If the ADP2164 junction temperature rises above 140°C, the
thermal shutdown circuit turns off the regulator. Extreme junc-
tion temperatures can be the result of high current operation,
poor circuit board design, and/or high ambient temperature.
When thermal shutdown occurs, a 15°C hysteresis ensures that
the ADP2164 does not return to operation until the on-chip
temperature falls below 125°C. Soft start is initiated when the
part comes out of thermal shutdown.
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