Effect of Temperature: Both capacitance and dissipa-

tion factor are affected by variations in temperature. The max-

imum capacitance change with temperature is defined by the

temperature characteristic. However, this only defines a “box”

bounded by the upper and lower operating temperatures and

the minimum and maximum capacitance values. Within this

“box”, the variation with temperature depends upon the spe-

cific dielectric formulation. Typical curves for KEMET capaci-

tors are shown in Figures 3, 4, and 5. These figures also

include the typical change in dissipation factor for KEMET

capacitors.

Insulation resistance decreases with temperature.

Typically, the insulation resistance at maximum rated temper-

ature is 10% of the 25°C value.

Effect of Voltage: Class I ceramic capacitors are not

affected by variations in applied AC or DC voltages. For Class

II and III ceramic capacitors, variations in voltage af

fect only

the capacitance and dissipation factor. The application of DC

voltage higher than 5 vdc reduces both the capacitance and

dissipation factor. The application of AC voltages up to 10-20

Vac tends to increase both capacitance and dissipation factor.

At higher AC voltages, both capacitance and dissipation factor

begin to decrease.

Typical curves showing the effect of applied AC and DC

voltage are shown in Figure 6 for KEMET X7R capacitors and

Figure 7 for KEMET Z5U capacitors.

fect of Frequency: Frequency affects both capaci-

tance and dissipation factor. Typical curves for KEMET multi-

layer ceramic capacitors are shown in Figures 8 and 9.

he variation of impedance with frequency is an impor-

tant consideration in the application of multilayer ceramic

capacitors. Total impedance of the capacitor is the vector of the

capacitive reactance, the inductive reactance, and the ESR, as

illustrated in Figure 2. As frequency increases, the capacitive

reactance decreases. However, the series inductance (L)

shown in Figure 1 produces inductive reactance, which

increases with frequency. At some frequency, the impedance

ceases to be capacitive and becomes inductive. This point, at

the bottom of the V-shaped impedance versus frequency

curves, is the self-resonant frequency. At the self-resonant fre-

quency, the reactance is zero, and the impedance consists of

the ESR only.

Typical impedance versus frequency curves for KEMET

multilayer ceramic capacitors are shown in Figures 10, 11, and

12. These curves apply to KEMET capacitors in chip form, with-

out leads. Lead configuration and lead length have a significant

impact on the series inductance. The lead inductance is

approximately 10nH/inch, which is large compared to the

inductance of the chip. The effect of this additional inductance

is a decrease in the self-resonant frequency, and an increase

in impedance in the inductive region above the self-resonant

frequency.

Effect of Time: The capacitance of Class II and III

dielectrics change with time as well as with temperature, volt-

age and frequency. This change with time is known as “aging.”

It is caused by gradual realignment of the crystalline structure

of the ceramic dielectric material as it is cooled below its Curie

temperature, which produces a loss of capacitance with time.

The aging process is predictable and follows a logarithmic

decay. Typical aging rates for C0G, X7R, and Z5U dielectrics

are as follows:

C0G None

X7R 2.0% per decade of time

Z5U 5.0% per decade of time

Typical aging curves for X7R and Z5U dielectrics are

shown in Figure 13.

The aging process is reversible. If the capacitor is heat-

ed to a temperature above its Curie point for some period of

time, de-aging will occur and the capacitor will regain the

capacitance lost during the aging process. The amount of de-

aging depends on both the elevated temperature and the

length of time at that temperature. Exposure to 150°C for one-

half hour or 125°C for two hours is usually sufficient to return

the capacitor to its initial value.

Because the capacitance changes rapidly immediately

after de-aging, capacitance measurements are usually delayed

for at least 10 hours after the de-aging process, which is often

referred to as the “last heat.” In addition, manufacturers utilize

the aging rates to set factory test limits which will bring the

capacitance within the specified tolerance at some future time,

to allow for customer receipt and use. Typically, the test limits

are adjusted so that the capacitance will be within the specified

tolerance after either 1,000 hours or 100 days, depending on

the manufacturer and the product type.

Application Notes

APPLICATION NOTES FOR MULTILAYER

CERAMIC CAPACITORS

APPLICATION NOTES FOR MULTILAYER

CERAMIC CAPACITORS

POWER DISSIPATION

Power dissipation has been empirically determined for

two representative KEMET series: C052 and C062. Power dis-

sipation capability for various mounting configurations is shown

in Table 3. This table was extracted from Engineering Bulletin

F-2013, which provides a more detailed treatment of this sub-

ject.

Note that no significant difference was detected between

the two sizes in spite of a 2 to 1 surface area ratio. Due to the

materials used in the construction of multilayer ceramic capac-

itors, the power dissipation capability does not depend greatly

on the surface area of the capacitor body, but rather on how

well heat is conducted out of the capacitor lead wires.

Consequently, this power dissipation capability is applicable to

other leaded multilayer styles and sizes.

TABLE 3

POWER DISSIPATION CAPABILITY

(Rise in Celsius degrees per Watt)

Power

Mounting Configuration Dissipation

of C052 & C062

1.00" leadwires attached to binding post 90 Celsius degrees

of GR-1615 bridge (excellent heat sink) rise per Watt ±10%

0.25" leadwires attached to binding post 55 Celsius degrees

of GR-1615 bridge rise per Watt ±10%

Capacitor mounted flush to 0.062" glass- 77 Celsius degrees

epoxy circuit board with small copper traces rise per Watt ±10%

Capacitor mounted flush to 0.062" glass- 53 Celsius degrees

epoxy circuit board with four square inches rise per Watt ±10%

of copper land area as a heat sink

As shown in Table 3, the power dissipation capability of

the capacitor is very sensitive to the details of its use environ-

ment. The temperature rise due to power dissipation should not

exceed 20°C. Using that constraint, the maximum permissible

power dissipation may be calculated from the data provided in

Table 3.

It is often convenient to translate power dissipation capa-

bility into a permissible AC voltage rating. Assuming a sinu-

soidal wave form, the RMS “ripple voltage” may be calculated

The data necessary to make this calculation is included in

Engineering Bulletin F-2013. However, the following criteria

must be observed:

1. The temperature rise due to power dissipation

should be limited to 20°C.

2. The peak AC voltage plus the DC voltage must not

exceed the maximum working voltage of the

capacitor.

Provided that these criteria are met, multilayer ceramic

E = Z x

Where E = RMS Ripple Voltage (volts)

P = Power Dissipation (watts)

Z = Impedance

R = ESR

MAX

capacitors may be operated with AC voltage applied without

need for DC bias.

RELIABILITY

A well constructed multilayer ceramic capacitor is

extremely reliable and, for all practical purposes, has an infi-

nite life span when used within the maximum voltage and

temperature ratings. Capacitor failure may be induced by sus-

tained operation at voltages that exceed the rated DC voltage,

voltage spikes or transients that exceed the dielectric with-

standing voltage, sustained operation at temperatures above

the maximum rated temperature, or the excessive tempera-

ture rise due to power dissipation.

Failure rate is usually expressed in terms of percent per

1,000 hours or in FITS (failure per billion hours). Some

KEMET series are qualified under U.S. military established

reliability specifications MIL-PRF-20, MIL-PRF-123, MIL-

PRF-39014, and MIL-PRF-55681. Failure rates as low as

0.001% per 1,000 hours are available for all capacitance /

voltage ratings covered by these specifications. These spec-

ifications and

accompanying Qualified Products List should

be consulted for details.

For series not covered by these military specifications,

an internal testing program is maintained by KEMET Quality

Assurance. Samples from each week’s production are sub-

jected to a 2,000 hour accelerated life test at 2 x rated voltage

and maximum rated temperature. Based on the results of

these tests, the average failure rate for all non-military series

covered by this test program is currently 0.06% per 1,000

hours at maximum rated conditions. The failure rate would be

much lower at typical use conditions. For example, using MIL-

HDBK-217D this failure rate translates to 0.9 FITS at 50%

rated voltage and 50°C.

Current failure rate details for specific KEMET multilay-

er ceramic capacitor series are available on request.

MISAPPLICATION

Ceramic capacitors, like any other capacitors, may fail

if they are misapplied. Typical misapplications include expo-

sure to excessive voltage, current or temperature. If the

dielectric layer of the capacitor is damaged by misapplication

the electrical energy of the circuit can be released as heat,

which may damage the circuit board and other components

as well.

If potential for misapplication exists, it is recommended

that precautions be taken to protect personnel and equipment

during initial application of voltage. Commonly used precau-

tions include shielding of personnel and sensing for excessive

power drain during board testing.

STORAGE AND HANDLING

Ceramic chip capacitors should be stored in normal

working environments. While the chips themselves are quite

robust in other environments, solderability will be degraded

by exposure to high temperatures, high humidity, corrosive

atmospheres, and long term storage. In addition, packaging

materials will be degraded by high temperature – reels may

soften or warp, and tape peel force may increase. KEMET

recommends that maximum storage temperature not exceed

40˚ C, and maximum storage humidity not exceed 70% rela-

tive humidity. In addition, temperature fluctuations should be

minimized to avoid condensation on the parts, and atmos-

pheres should be free of chlorine and sulfur bearing com-

pounds. For optimized solderability, chip stock should be

used promptly, preferably within 1.5 years of receipt.

from the following formula:

IMPEDANCE VS FREQUENCY

Impedance (Ohms)

110100 1,000

.001

0.01

100

0.1

Frequency - MHz

Impedance vs Frequency for C0G Dielectric

Figure 10.

EFFECT OF FREQUENCY

-0.1

0.2

-0.2

+0.1

0.10

0.20

0.0

Frequency - Hertz

Capacitance & DF vs Frequency - C0G

Figure 8.

%DF

Typical Aging Rates for X7R & Z5UFigure 13.

74%

76%

78%

80%

82%

84%

86%

88%

90%

92%

94%

96%

98%

100%

Capacitance

110100 1000 10K 100K

EFFECT OF TIME

%DF

-10

-15

10.0

0.0

2.5

7.5

Frequency - Hertz

Capacitance & DF vs Frequency - X7R & Z5U

Figure 9.

.01μF

.001μF

%Δ

1001K 10K 100K1M 10M

001K 10K 100K1M 10M

%ΔC

%DF

Z5U

X7R

%DF

ΔC

Impedance (Ohms)

110100 1,000

0.001

0.01

100

0.1

Frequency - MHz

Impedance vs Frequency for Z5U Dielectric

Figure 12.

Impedance (Ohms)

110100 1,000

0.001

0.01

0.1

Frequency - MHz

Impedance vs Frequency for X7R Dielectric

Figure 11.

0.1μF

1.0 μF

0.1μF

.01μF

1.0 μF

Impedance vs. Frequency

eaded Ceramic C0G

0.01

0.1

100

0.1 1 1 0 100 1000

requency - MHz

Impedance (Ohms)

0.01µF

.001µF

Leaded X7R

.01

0.1

100

0.1 1 1 0 100 1000

Frequency - MHz

Impedance (Ohms)

0.01

0.1

mpedance vs. Frequency

1.0

Impedance vs. Frequency

Leaded Z5U

0.01

0.1

100

0.1 1 1 0 100 1000

Frequency - MHz

Impedance (Ohms)

Impedance vs Frequency

for C0G Dielectric

Figure 10.

Impedance vs Frequency

for Z5U Dielectric

Figure 12.

Impedance vs Frequency

for X7R Dielectric

Figure 11.

Impedance vs Frequency

for C0G Dielectric

Figure 10.

Impedance vs Frequency

for Z5U Dielectric

Figure 12.

Impedance vs Frequency

for X7R Dielectric

Figure 11.

Impedance vs Frequency

for C0G Dielectric

Figure 10.

Impedance vs Frequency

for Z5U Dielectric

Figure 12.

Impedance vs Frequency

for X7R Dielectric

Figure 11.

Capacitance

100%

74%

76%

78%

80%

82%

84%

86%

88%

90%

92%

94%

96%

98%

X7R

Z5U

1 10 100 1000 10K 100K

Application Notes

APPLICATION NOTES FOR MULTILAYER

CERAMIC CAPACITORS

Impedance vs Frequency

for C0G Dielectric

Figure 10.

Impedance vs Frequency

for Z5U Dielectric

Figure 12.

Impedance vs Frequency

for X7R Dielectric

Figure 11.

mpedance vs Frequency

for C0G Dielectric

igure 10.

Impedance vs Frequency

for Z5U Dielectric

Figure 12.

Impedance vs Frequency

for X7R Dielectric

Figure 11.

mpedance vs Frequency

or C0G Dielectric

igure 10.

Impedance vs Frequency

for Z5U Dielectric

Figure 12.

Impedance vs Frequency

for X7R Dielectric

Figure 11.

(hours)

Part #	C315C103K5R5CA
Description	Cap Ceramic 0.01uF 50V X7R 10% Radial 2.54mm 125C Bulk Additional Information:
Category	CAPACITOR
Availability	In Stock
Qty	10

C315C103K5R5CA

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