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C2012C0G1H101J

Part # C2012C0G1H101J
Description Cap Ceramic 100pF 50V C0G 5%SMD 0805 125C
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TDK Corporation
Date Code: 1021
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

LM5020
www.ti.com
SNVS275F MAY 2004REVISED APRIL 2006
DETAILED OPERATING DESCRIPTION
The LM5020 High Voltage PWM controller contains all of the features needed to implement single ended primary
power converter topologies. The LM5020 includes a high-voltage startup regulator that operates over a wide
input range to 100V. The PWM controller is designed for high speed capability including an oscillator frequency
range to 1MHz and total propagation delays less than 100ns. Additional features include an error amplifier,
precision reference, line under-voltage lockout, cycle-by-cycle current limit, slope compensation, softstart,
oscillator sync capability and thermal shutdown. The functional block diagram of the LM5020 is shown in Figure
1. The LM5020 is designed for current-mode control power converters, which require a single drive output, such
as Flyback and Forward topologies. The LM5020 provides all of the advantages of current-mode control
including line feed-forward, cycle-by-cycle current limiting and simplified loop compensation .
High Voltage Start-Up Regulator
The LM5020 contains an internal high voltage startup regulator, that allows the input pin (Vin) to be connected
directly to line voltages as high as 100V. The regulator output is internally current limited to 15mA. When power
is applied, the regulator is enabled and sources current into an external capacitor connected to the V
CC
pin. The
recommended capacitance range for the Vcc regulator is 0.1µF to 100µF. When the voltage on the V
CC
pin
reaches the regulation level of 7.7V, the controller output is enabled. The controller will remain enabled until V
CC
falls below 6V.
In typical applications, a transformer auxiliary winding is connected through a diode to the V
CC
pin. This winding
should raise the V
CC
voltage above 8V to shut off the internal startup regulator. Powering V
CC
from an auxiliary
winding improves conversion efficiency while reducing the power dissipated in the controller. The external V
CC
capacitor must be selected such that the capacitor maintains the Vcc voltage greater than the V
CC
UVLO falling
threshold (6V) during the initial start-up. During a fault condition when the converter auxiliary winding is inactive,
external current draw on the V
CC
line should be limited such that the power dissipated in the start-up regulator
does not exceed the maximum power dissipation capability of the controller.
An external start-up or other bias rail can be used instead of the internal start-up regulator by connecting the V
CC
and the Vin pins together and feeding the external bias voltage (8-15V) to the two pins.
Line Under Voltage Detector
The LM5020 contains a line Under Voltage Lock Out (UVLO) circuit. An external set-point voltage divider from
Vin to GND sets the operational range of the converter. The resistor divider must be designed such that the
voltage at the UVLO pin is greater than 1.25V when Vin is in the desired operating range. If the under voltage
threshold is not met, all functions of the controller are disabled and the controller remains in a low power standby
state.
UVLO hysteresis is accomplished with an internal 20µA current source that is switched on or off into the
impedance of the set-point divider. When the UVLO threshold is exceeded, the current source is activated to
instantly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the 1.25V threshold the
current source is turned off, causing the voltage at the UVLO pin to fall. The UVLO pin can also be used to
implement a remote enable / disable function. If an external transistor pulls the UVLO pin below the 1.25V
threshold, the converter is disabled.
Error Amplifier
An internal high gain error amplifier is provided within the LM5020. The amplifier's non-inverting input is internally
set to a fixed reference voltage of 1.25V. The inverting input is connected to the FB pin. In non-isolated
applications, the power converter output is connected to the FB pin via voltage scaling resistors. Loop
compensation components are connected between the COMP and FB pins. For most isolated applications the
error amplifier function is implemented on the secondary side of the converter and the internal error amplifier is
not used. The internal error amplifier is configured as an open drain output and can be disabled by connecting
the FB pin to ground. An internal 5K pull-up resistor between a 5V reference and COMP can be used as the pull-
up for an optocoupler in isolated applications.
Copyright © 2004–2006, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: LM5020
RT =
1
F x 316 x 10
-12
RT =
1
F x 158 x 10
-12
LM5020
SNVS275F MAY 2004REVISED APRIL 2006
www.ti.com
Current Limit/Current Sense
The LM5020 provides a cycle-by-cycle over current protection function. Current limit is accomplished by an
internal current sense comparator. If the voltage at the current sense comparator input exceeds 0.5V, the output
is immediately terminated. A small RC filter, located near the controller, is recommended to filter noise from the
current sense signal. The CS input has an internal MOSFET which discharges the CS pin capacitance at the
conclusion of every cycle. The discharge device remains on an additional 50ns after the beginning of the new
cycle to attenuate the leading edge spike on the current sense signal.
The LM5020 current sense and PWM comparators are very fast, and may respond to short duration noise
pulses. Layout considerations are critical for the current sense filter and sense resistor. The capacitor associated
with the CS filter must be located very close to the LM5020 and connected directly to the pins of the controller
(CS and GND). If a current sense transformer is used, both leads of the transformer secondary should be routed
to the sense resistor and the current sense filter network. A sense resistor located in the source of the primary
power MOSFET may be used for current sensing, but a low inductance resistor is required. When designing with
a current sense resistor all of the noise sensitive low power ground connections should be connected together
local to the controller and a single connection should be made to the high current power ground (sense resistor
ground point).
Oscillator and Sync Capability
A single external resistor connected between the RT and GND pins sets the LM5020 oscillator frequency.
Internal to the LM5020-2 device (50% duty cycle limited option) is an oscillator divide by two circuit. This divide
by two circuit creates an exact 50% duty cycle pulse which is used internally to create a precise 50% duty cycle
limit function. Because of this, the internal oscillator actually operates at twice the frequency of the output (OUT).
For the LM5020-1 device the oscillator frequency and the operational output frequency are the same. To set a
desired output operational frequency (F), the RT resistor can be calculated from:
LM5020-1:
(1)
LM5020-2:
(2)
The LM5020 can also be synchronized to an external clock. The external clock must have a higher frequency
than the free running oscillator frequency set by the RT resistor. The clock signal should be capacitively coupled
into the RT pin through a 100pF capacitor. A peak voltage level greater than 3.7 Volts at the RT pin is required
for detection of the sync pulse. The sync pulse width should be set between 15 to 150ns by the external
components. The RT resistor is always required, whether the oscillator is free running or externally synchronized.
The voltage at the RT pin is internally regulated at 2 Volts. The RT resistor should be located very close to the
device and connected directly to the pins of the controller (RT and GND).
PWM Comparator / Slope Compensation
The PWM comparator compares the current ramp signal with the loop error voltage derived from the error
amplifier output. The error amplifier output voltage at the COMP pin is offset by 1.4V and then further attenuated
by a 3:1 resistor divider. The PWM comparator polarity is such that 0 Volts on the COMP pin will result in a zero
duty cycle at the controller output. For duty cycles greater than 50 percent, current mode control circuits are
subject to sub-harmonic oscillation. By adding an additional fixed slope voltage ramp signal (slope compensation)
to the current sense signal, this oscillation can be avoided. The LM5020-1 integrates this slope compensation by
summing a current ramp generated by the oscillator with the current sense signal. Additional slope compensation
may be added by increasing the source impedance of the current sense signal. Since the LM5020-2 is not
capable of duty cycles greater than 50%, there is no slope compensation feature in this device.
8 Submit Documentation Feedback Copyright © 2004–2006, Texas Instruments Incorporated
Product Folder Links: LM5020
LM5020
C5
0.01 PF
SS
R6
12.4k
GND GND
C8
100 pF
RT/
SYNC
10
9
3
U1
GND
6
FB
2
CS
8
100
R7
C11
1000 pF
R8
0.47
R9
0.47
GND GND GND
OUT
5
UVLO
7
VIN
1
VCC
4
C10
4.7 PF
C4
0.1 PF
GNDGND
R1
10
R4
1.00k
R2
61.9k
C2
2.2 PF
GND
C1
2.2 PF
GND
Shutdown
C3
0.01 PF
GND
R3
2.87k
GND
V+
1
J1
30-75V IN
3
2
1
4
Q1
Si7898DP
6
7
8
5
GND
D1
CMPD2838E
Z1
1SMB5936B
GND
T1
D3
MBRD835L
D2
CMPD2838E
20
R13
GND
C12
470 pF
10, 1W
R10
GND
R12
1.47k
R11
2.43k
0.1 PF
C9
GND
OUT RTN
1
2
GND
GND
2
J2
+3.3V
C13
100 PF
GND
C14
100 PF
GND
C15
270 PF
GND
COMP
SYNC
Input
R5
15.0k
C7
3300 pF
C6
220 pF
LM5020
www.ti.com
SNVS275F MAY 2004REVISED APRIL 2006
Soft Start
The softstart feature allows the power converter to gradually reach the initial steady state operating point, thereby
reducing start-up stresses and current surges. At power on, after the V
CC
and the line undervoltage lockout
thresholds are satisfied, an internal 10µA current source charges an external capacitor connected to the SS pin.
The capacitor voltage will ramp up slowly and will limit the COMP pin voltage and the duty cycle of the output
pulses.
Gate Driver and Maximum Duty Cycle Limit
The LM5020 provides an internal gate driver (OUT), which can source and sink a peak current of 1 Amp. The
LM5020 is available in two duty cycle limit options. The maximum output duty cycle is typically 80% for the
LM5020-1 option and precisely equal to 50% for the LM5020-2 option. The maximum duty cycle function for the
LM5020-2 is accomplished with an internal toggle flip-flop which ensures an accurate duty cycle limit. The
internal oscillator frequency of the LM5020-2 is therefore twice the operating frequency of the PWM controller
(OUT pin).
The 80% maximum duty cycle limit of the LM5020-1 is determined by the internal oscillator and varies more than
the 50% limit of the LM5020-2. For the LM5020-1 the internal oscillator frequency and the operational frequency
of the PWM controller are equal.
Thermal Protection
Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event the maximum junction
temperature is exceeded. This feature prevents catastrophic failures from accidental device overheating. When
activated, typically at 165 degrees Celsius, the controller is forced into a low power standby state, disabling the
output driver and the bias regulator. After the temperature is reduced (typical hysteresis = 25°C) the V
CC
regulator is enabled and a softstart sequence initiated.
Typical Application Circuit: 36V - 75 V
IN
and 3.3V, 4.5A OUT
Copyright © 2004–2006, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: LM5020
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