OUT

COMP

UVLO

VIN

VCC

COMPENSATION

GND

OUT

LM5020

RT SYNC

LM5020

www.ti.com

SNVS275F –MAY 2004–REVISED APRIL 2006

LM5020 100V Current Mode PWM Controller

Check for Samples: LM5020

FEATURES

PACKAGES

• Internal Start-up Bias Regulator

• VSSOP-10

• Error Amplifier • WSON-10 (4 mm x 4 mm)

• Precision Voltage Reference

DESCRIPTION

• Programmable Softstart

The LM5020 high voltage pulse-width-modulation

• 1A Peak Gate Driver

(PWM) controller contains all of the features needed

• Maximum Duty Cycle Limiting (80% for

to implement single ended primary power converter

LM5020-1 or 50% for LM5020-2)

topologies. Output voltage regulation is based on

current-mode control, which eases the design of loop

• Programmable Line Under Voltage Lockout

compensation while providing inherent line feed-

(UVLO) with Adjustable Hysteresis

forward. The LM5020 includes a high-voltage start-up

• Cycle-by-Cycle Over-Current Protection

regulator that operates over a wide input range up to

• Slope Compensation (LM5020-1)

100V. The PWM controller is designed for high speed

capability including an oscillator frequency range to

• Programmable Oscillator Frequency with

1MHz and total propagation delays less than 100ns.

Synchronization Capability

Additional features include an error amplifier,

• Current Sense Leading Edge Blanking

precision reference, line under-voltage lockout, cycle-

• Thermal Shutdown Protection

by-cycle current limit, slope compensation, softstart,

oscillator synchronization capability and thermal

shutdown. The controller is available in both VSSOP-

APPLICATIONS

10 and WSON-10 packages.

• Telecommunication Power Converters

• Industrial Power Converters

• +42V Automotive Systems

Typical Application Circuit

Figure 1. Non-Isolated Flyback Converter

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

VCC

OUT

VIN

COMP

UVLO

GND

RT/SYNC

LM5020

SNVS275F –MAY 2004–REVISED APRIL 2006

www.ti.com

Connection Diagram

Top View

Figure 2. 10-Lead VSSOP, WSON

PIN DESCRIPTIONS

Pin Name Description Application Information

1 VIN Source Input Voltage Input to the start-up regulator. Input range is 13V to 100V.

2 FB Feedback Signal Inverting input of the internal error amplifier. The non-

inverting input is internally connected to a 1.25V reference.

3 COMP The output of the error amplifier and input to the COMP pull-up is provided by an internal 5K resistor which

Pulse Width Modulator may be used to bias an opto-coupler transistor.

4 VCC Output of the internal high voltage series pass If an auxiliary winding raises the voltage on this pin above

regulator. Regulated output voltage is 7.7V the regulation set point, the internal series pass regulator

will shut down, reducing the internal power dissipation.

5 OUT Output of the PWM controller Gate driver output with a 1A peak current capability.

6 GND Ground return

7 UVLO Line Under-Voltage Shutdown An external resistor divider from the power converter

source voltage sets the shutdown levels. The threshold at

this pin is 1.25V. Hysteresis is set by a switched internal

20µA current source.

8 CS Current Sense input Current sense input for current mode control and over-

current protection. Current limiting is accomplished using a

dedicated current sense comparator. If the CS pin voltage

exceeds 0.5V the OUT pin switches low for cycle-by-cycle

current limiting. CS is held low for 50ns after OUT switches

high to blank leading edge current spikes.

9 RT / SYNC Oscillator timing resistor pin and synchronization An external resistor connected from RT to GND sets the

input oscillator frequency. This pin also accepts synchronization

pulses from an external clock.

10 SS Softstart Input An external capacitor and an internal 10µA current source

set the soft-start ramp rate.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Product Folder Links: LM5020

LM5020

www.ti.com

SNVS275F –MAY 2004–REVISED APRIL 2006

Absolute Maximum Ratings

(1)(2)

VIN to GND -0.3V to 100V

VCC to GND -0.3V to 16V

RT to GND -0.3V to 5.5V

All other pins to GND -0.3V to 7V

Power Dissipation Internally Limited

ESD Rating

(3)

Human Body Model 2kV

Storage Temperature -65°C to +150°C

Junction Temperature 150°C

(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which

operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(3) The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor.

Operating Ratings

VIN Voltage 13V to 90V

External Voltage applied to VCC 8V to 15V

Operating Junction Temperature -40°C to +125°C

Electrical Characteristics

Specifications in standard type face are for T

= +25°C and those in boldface type apply over the full operating junction

temperature range. Unless otherwise specified: VIN = 48V, VCC = 10V, and RT = 31.6kΩ.

(1)

Symbol Parameter Conditions Min Typ Max Units

Startup Regulator

Reg V

Regulation V

= Open 7.4 7.7 8.0 V

Current Limit See

(2)

15 22 mA

I-V

Startup Regulator Leakage V

= 100V 150 500 µA

Shutdown Current V

UVLO

= 0V, V

= open 250 350 µA

VCC Supply

UVLO (Rising) VccReg VccReg - V

- 300mV 100mV

UVLO (Falling) 5.3 6.0 6.7 V

Supply Current Cload = 0 2 3 mA

Error Amplifier

GBW Gain Bandwidth 4 MHz

DC Gain 75 dB

Reference Voltage FB = COMP 1.225 1.25 1.275 V

COMP Sink Capability FB = 1.5V COMP= 1V 5 17 mA

UVLO Pin

Shutdown Threshold 1.225 1.25 1.275 V

Undervoltage Shutdown Hysteresis 16 20 24 µA

Current Source

Current Limit

ILIM Delay to Output CS step from 0 to 0.6V 30 ns

Time to onset of OUT

Transition (90%)

Cycle by Cycle CS Threshold 0.45 0.5 0.55 V

Voltage

Leading Edge Blanking Time 50 ns

(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using

Statistical Quality Control (SQC) methods. The limits are used to calculate National's Average Outgoing Quality Level (AOQL).

(2) Device thermal limitations may limit usable range.

Product Folder Links: LM5020

Part #	C2012C0G1H101J
Description	Cap Ceramic 100pF 50V C0G 5%SMD 0805 125C Additional Information:
Category	CAPACITOR
Availability	In Stock
Qty	359

C2012C0G1H101J

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