SEMICONDUCTOR TECHNICAL DATA
3–89
REV 5
Motorola, Inc. 1996
3/93
The MC10125 is a quad translator for interfacing data and control signals
between the MECL section and saturated logic sections of digital systems. The
MC10125 incorporates differential inputs and Schottky TTL “totem pole”
outputs. Differential inputs allow for use as an inverting/ non–inverting translator
or as a differential line receiver. The V
BB
reference voltage is available on pin 1
for use in single–ended input biasing. The outputs of the MC10125 go to a low
logic level whenever the inputs are left floating.
Power supply requirements are ground, +5.0 Volts and –5.2 Volts.
Propagation delay of the MC10125 is typically 4.5 ns. The MC10125 has fanout
of 10 TTL loads. The dc levels are MECL 10,000 in and Schottky TTL, or TTL
out. This device has an input common mode noise rejection of
± 1.0 Volt.
An advantage of this device is that MECL level information can be received,
via balanced twisted pair lines, in the TTL equipment. This isolates the MECL
logic from the noisy TTL environment. This device is useful in computers,
instrumentation, peripheral controllers, test equipment and digital
communications systems.
P
D
= 380 mW typ/pkg (No Load)
t
pd
= 4.5 ns typ (50% to + 1.5 Vdc out)
t
r
, t
f
= 2.5 ns typ (1.0 V to 2.0 V)
LOGIC DIAGRAM
4
3
2
5
7
6
12
11
10
13
15
14
1
V
BB
*
*V
BB
to be used to supply bias to the MC10125 only and bypassed (when used)
with 0.01 µF to 0.1 µF capacitor to ground (0 V). V
BB
can source < 1.0 mA.
When the input pin with the bubble goes positive, the output goes negative.
Gnd = PIN 16
V
CC
(+5.0Vdc) = PIN 9
V
EE
(–5.2Vdc) = PIN 8
DIP
PIN ASSIGNMENT
V
BB
A
IN
A
IN
A
OUT
B
OUT
B
IN
B
IN
V
EE
GND
D
IN
D
IN
D
OUT
C
OUT
C
IN
C
IN
V
CC
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
