ACTEL A54SX32-1PQ208I

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Item Description: IC FPGA 174 I/O 208QFP

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ACTEL 0415
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

June 2003 1
© 2003 Actel Corporation
v3.1
54SX Family FPGAs
Leading Edge Performance
320 MHz Internal Performance
3.7 ns Clock-to-Out (Pin-to-Pin)
0.1 ns Input Set-Up
0.25 ns Clock Skew
Specifications
12,000 to 48,000 System Gates
Up to 249 User-Programmable I/O Pins
Up to 1080 Flip-Flops
0.35µ CMOS
Features
66 MHz PCI
CPLD and FPGA Integration
Single Chip Solution
100% Resource Utilization with 100% Pin Locking
3.3V Operation with 5.0V Input Tolerance
Very Low Power Consumption
Deterministic, User-Controllable Timing
Unique In-System Diagnostic and Debug capability with
Silicon Explorer II
Boundary Scan Testing in Compliance with IEEE Standard
1149.1 (JTAG)
Secure Programming Technology Prevents Reverse
Engineering and Design Theft
SX Product Profile
A54SX08 A54SX16 A54SX16P A54SX32
Capacity
Typical Gates
System Gates
8,000
12,000
16,000
24,000
16,000
24,000
32,000
48,000
Logic Modules
Combinatorial Cells
768
512
1,452
924
1,452
924
2,880
1800
Register Cells (Dedicated Flip-Flops) 256 528 528 1,080
Maximum User I/Os 130 175 175 249
Clocks 3333
JTAG YesYesYesYes
PCI ——Yes
Clock-to-Out 3.7 ns 3.9 ns 4.4 ns 4.6 ns
Input Set-Up (External) 0.8 ns 0.5 ns 0.5 ns 0.1 ns
Speed Grades Std, –1, –2, –3 Std, –1, –2, –3 Std, –1, –2, –3 Std, –1, –2, –3
Temperature Grades C, I, M C, I, M C, I, M C, I, M
Packages (by pin count)
PLCC
PQFP
VQFP
TQFP
PBGA
FBGA
84
208
100
144, 176
144
208
100
176
208
100
144, 176
208
144, 176
313, 329
54SX Family FPGAs
2 v3.1
General Description
Actel’s SX family of FPGAs features a sea-of-modules
architecture that delivers device performance and
integration levels not currently achieved by any other FPGA
architecture. SX devices greatly simplify design time, enable
dramatic reductions in design costs and power
consumption, and further decrease time to market for
performance-intensive applications.
Actel’s SX architecture features two types of logic modules,
the combinatorial cell (C-cell) and the register cell (R-cell),
each optimized for fast and efficient mapping of synthesized
logic functions. The routing and interconnect resources are
in the metal layers above the logic modules, providing
optimal use of silicon. This enables the entire floor of the
device to be spanned with an uninterrupted grid of
fine-grained, synthesis-friendly logic modules (or
“sea-of-modules”), which reduces the distance signals have
to travel between logic modules. To minimize signal
propagation delay, SX devices employ both local and general
routing resources. The high-speed local routing resources
(DirectConnect and FastConnect) enable very fast local
signal propagation that is optimal for fast counters, state
machines, and datapath logic. The general system of
segmented routing tracks allows any logic module in the
array to be connected to any other logic or I/O module.
Within this system, propagation delay is minimized by
limiting the number of antifuse interconnect elements to
five (90 percent of connections typically use only three
antifuses). The unique local and general routing structure
featured in SX devices gives fast and predictable
performance, allows 100 percent pin-locking with full logic
utilization, enables concurrent PCB development, reduces
design time, and allows designers to achieve performance
goals with minimum effort.
Further complementing SX’s flexible routing structure is a
hard-wired, constantly loaded clock network that has been
tuned to provide fast clock propagation with minimal clock
skew. Additionally, the high performance of the internal
logic has eliminated the need to embed latches or flip-flops
in the I/O cells to achieve fast clock-to-out or fast input
set-up times. SX devices have easy-to-use I/O cells that do
not require HDL instantiation, facilitating design re-use and
reducing design and verification time.
Ordering Information
Application (Temperature Range)
Blank = Commercial (0 to +70°C)
I = Industrial (–40 to +85°C)
M = Military (–55 to +125°C)
PP = Pre-production
Package Type
BG = Ball Grid Array
PL = Plastic Leaded Chip Carrier
PQ = Plastic Quad Flat Pack
TQ = Thin (1.4 mm) Quad Flat Pack
VQ = Very Thin (1.0 mm) Quad Flat Pack
FG = Fine Pitch Ball Grid Array (1.0 mm)
Speed Grade
Blank = Standard Speed
–1 = Approximately 15% Faster than Standard
–2 = Approximately 25% Faster than Standard
–3 = Approximately 35% Faster than Standard
Part Number
A54SX08 = 12,000 System Gates
A54SX16 = 24,000 System Gates
A54SX16P = 24,000 System Gates
A54SX32 = 48,000 System Gates
Package Lead Count
A54SX16 PQ 208
2
Blank = Not PCI Compliant
P = PCI Compliant
P
v3.1 3
54SX Family FPGAs
Product Plan
Speed Grade* Application
Std1–2–3 C I
M
A54SX08 Device
84-Pin Plastic Leaded Chip Carrier (PLCC) ✔✔✔✔ ✔✔
100-Pin Very Thin Plastic Quad Flat Pack (VQFP) ✔✔✔✔ ✔✔
144-Pin Thin Quad Flat Pack (TQFP) ✔✔✔✔ ✔✔
144-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔✔✔ ✔✔
176-Pin Thin Quad Flat Pack (TQFP) ✔✔✔✔ ✔✔
208-Pin Plastic Quad Flat Pack (PQFP) ✔✔✔✔ ✔✔
A54SX16 Device
100-Pin Very Thin Plastic Quad Flat Pack (VQFP) ✔✔✔✔ ✔✔P
176-Pin Thin Quad Flat Pack (TQFP) ✔✔✔✔ ✔✔P
208-Pin Plastic Quad Flat Pack (PQFP) ✔✔✔✔ ✔✔P
A54SX16P Device
100-Pin Very Thin Plastic Quad Flat Pack (VQFP) ✔✔✔✔ ✔✔
144-Pin Thin Quad Flat Pack (TQFP) ✔✔✔✔ ✔✔
176-Pin Thin Quad Flat Pack (TQFP) ✔✔✔✔ ✔✔
208-Pin Plastic Quad Flat Pack (PQFP) ✔✔✔✔ ✔✔
A54SX32 Device
144-Pin Thin Quad Flat Pack (TQFP) ✔✔✔✔ ✔✔P
176-Pin Thin Quad Flat Pack (TQFP) ✔✔✔✔ ✔✔P
208-Pin Plastic Quad Flat Pack (PQFP) ✔✔✔✔ ✔✔P
313-Pin Plastic Ball Grid Array (PBGA) ✔✔✔✔ ✔✔
329-Pin Plastic Ball Grid Array (PBGA) ✔✔✔✔ ✔✔
Contact your Actel sales representative for product availability.
Applications:C = CommercialAvailability: = Available*Speed Grade:–1 = Approx. 15% faster than Standard
I = Industrial P = Planned –2 = Approx. 25% faster than Standard
M = Military = Not Planned –3 = Approx. 35% faster than Standard
Only Std, –1, –2 Speed Grade
Only Std, –1 Speed Grade
Plastic Device Resources
User I/Os (including clock buffers)
Device
PLCC
84-Pin
VQFP
100-Pin
PQFP
208-Pin
TQFP
144-Pin
TQFP
176-Pin
PBGA
313-Pin
PBGA
329-Pin
FBGA
144-Pin
A54SX08 69 81 130 113 128 111
A54SX16 81 175 147
A54SX16P 81 175 113 147
A54SX32 174 113 147 249 249
Package Definitions (Consult your local Actel sales representative for product availability.)
PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, VQFP = Very Thin Quad Flat Pack,
PBGA = Plastic Ball Grid Array, FBGA = Fine Pitch (1.0 mm) Ball Grid Array
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