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8A/S6

Part # 8A/S6
Description Incandescent S Light Lamp
Category LAMP
Availability In Stock
Qty 2
Qty Price
1 + $2.43518
Manufacturer Available Qty
General Electric
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Clock Generator Module (CGM)
Technical Data MC68HC908AZ60A — Rev 2.0
196 Clock Generator Module (CGM) MOTOROLA
MC68HC908AZ60A — Rev 2.0 Technical Data
MOTOROLA Configuration Register (CONFIG-1) 197
Technical Data — MC68HC908AZ60A
Section 11. Configuration Register (CONFIG-1)
11.1 Contents
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
11.3 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
11.2 Introduction
This section describes the configuration register (CONFIG-1), which
contains bits that configure these options:
Resets caused by the LVI module
Power to the LVI module
LVI enabled during stop mode
Stop mode recovery time (32 CGMXCLK cycles or 4096
CGMXCLK cycles)
Computer operating properly module (COP)
Stop instruction enable/disable.
11.3 Functional Description
The configuration register is a write-once register. Out of reset, the
configuration register will read the default value. Once the register is
written, further writes will have no effect until a reset occurs.
NOTE: If the LVI module and the LVI reset signal are enabled, a reset occurs
when V
DD
falls to a voltage, LVI
TRIPF
, and remains at or below that level
Configuration Register (CONFIG-1)
Technical Data MC68HC908AZ60A — Rev 2.0
198 Configuration Register (CONFIG-1) MOTOROLA
for at least nine consecutive CPU cycles. Once an LVI reset occurs, the
MCU remains in reset until V
DD
rises to a voltage, LVI
TRIPR
.
LVISTOP — LVI Stop Mode Enable Bit
LVISTOP enables the LVI module in stop mode. (See Low Voltage
Inhibit (LVI) on page 229).
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
NOTE: To have the LVI enabled in stop mode, the LVIPWR must be at a logic 1
and the LVISTOP bit must be at a logic 1. Take note that by enabling the
LVI in stop mode, the stop I
DD
current will be higher.
LVIRST — LVI Reset Enable Bit
LVIRST enables the reset signal from the LVI module. (See Low
Voltage Inhibit (LVI) on page 229).
1 = LVI module resets enabled
0 = LVI module resets disabled
Address: $001F
Bit 7654321Bit 0
Read:
LVISTOP R LVIRST LVIPWR SSREC COPL STOP COPD
Write:
Reset:01110000
R=Reserved
Figure 11-1. Configuration Register (CONFIG-1)
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