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8A/S6

Part # 8A/S6
Description Incandescent S Light Lamp
Category LAMP
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Clock Generator Module (CGM)
Acquisition/Lock Time Specifications
MC68HC908AZ60A — Rev 2.0 Technical Data
MOTOROLA Clock Generator Module (CGM) 193
Temperature and processing also can affect acquisition time because
the electrical characteristics of the PLL change. The part operates as
specified as long as these influences stay within the specified limits.
External factors, however, can cause drastic changes in the operation of
the PLL. These factors include noise injected into the PLL through the
filter capacitor, filter capacitor leakage, stray impedances on the circuit
board, and even humidity or circuit board contamination.
10.10.3 Choosing a Filter Capacitor
As described in Parametric Influences on Reaction Time on page
192, the external filter capacitor, C
F
, is critical to the stability and reaction
time of the PLL. The PLL is also dependent on reference frequency and
supply voltage. The value of the capacitor must, therefore, be chosen
with supply potential and reference frequency in mind. For proper
operation, the external filter capacitor must be chosen according to this
equation:
For acceptable values of C
fact
, (see Electrical Specifications on page
530). For the value of V
DDA
, choose the voltage potential at which the
MCU is operating. If the power supply is variable, choose a value near
the middle of the range of possible supply values.
This equation does not always yield a commonly available capacitor
size, so round to the nearest available size. If the value is between two
different sizes, choose the higher value for better stability. Choosing the
lower size may seem attractive for acquisition time improvement, but the
PLL may become unstable. Also, always choose a capacitor with a tight
tolerance (±20% or better) and low dissipation.
10.10.4 Reaction Time Calculation
The actual acquisition and lock times can be calculated using the
equations below. These equations yield nominal values under the
following conditions:
C
F
C
fact
V
DDA
fCGMRDV
-------------------


=
Clock Generator Module (CGM)
Technical Data MC68HC908AZ60A — Rev 2.0
194 Clock Generator Module (CGM) MOTOROLA
Correct selection of filter capacitor, C
F
(see Choosing a Filter
Capacitor on page 193).
Room temperature operation
Negligible external leakage on CGMXFC
Negligible noise
The K factor in the equations is derived from internal PLL parameters.
K
acq
is the K factor when the PLL is configured in acquisition mode, and
K
trk
is the K factor when the PLL is configured in tracking mode. (See
Acquisition and Tracking Modes on page 175).
Note the inverse proportionality between the lock time and the reference
frequency.
In automatic bandwidth control mode, the acquisition and lock times are
quantized into units based on the reference frequency. (See Manual
and Automatic PLL Bandwidth Modes on page 175). A certain
number of clock cycles, n
ACQ
, is required to ascertain that the PLL is
within the tracking mode entry tolerance,
TRK
, before exiting acquisition
mode. A certain number of clock cycles, n
TRK
, is required to ascertain
that the PLL is within the lock mode entry tolerance,
Lock
. Therefore, the
acquisition time, t
ACQ
, is an integer multiple of n
ACQ
/f
CGMRDV
, and the
acquisition to lock time, t
AL
, is an integer multiple of n
TRK
/f
CGMRDV
. Also,
since the average frequency over the entire measurement period must
be within the specified tolerance, the total time usually is longer than
t
Lock
as calculated above.
t
acq
V
DDA
f
CGMRDV
--------------------


8
K
ACQ
-------------


=
t
al
V
DDA
f
CGMRDV
--------------------


4
K
TRK
------------


=
t
Lock
t
ACQ
t
AL
+=
Clock Generator Module (CGM)
Acquisition/Lock Time Specifications
MC68HC908AZ60A — Rev 2.0 Technical Data
MOTOROLA Clock Generator Module (CGM) 195
In manual mode, it is usually necessary to wait considerably longer than
t
Lock
before selecting the PLL clock (see Base Clock Selector Circuit
on page 179), because the factors described in Parametric Influences
on Reaction Time on page 192, may slow the lock time considerably.
When defining a limit in software for the maximum lock time, the value
must allow for variation due to all of the factors mentioned in this section,
especially due to the C
F
capacitor and application specific influences.
The calculated lock time is only an indication and it is the customer’s
responsibility to allow enough of a guard band for their application. Prior
to finalizing any software and while determining the maximum lock time,
take into account all device to device differences. Typically, applications
set the maximum lock time as an order of magnitude higher than the
measured value. This is considered sufficient for all such device to
device variation.
Motorola recommends measuring the lock time of the application system
by utilizing dedicated software, running in FLASH, EEPROM or RAM.
This should toggle a port pin when the PLL is first configured and
switched on, then again when it goes from acquisition to lock mode and
finally again when the PLL lock bit is set. The resultant waveform can be
captured on an oscilloscope and used to determine the typical lock time
for the microcontroller and the associated external application circuit.
e.g.
NOTE: The filter capacitor should be fully discharged prior to making any
measurements.
t
LOCK
t
ACQ
t
AL
t
TRK
Complete and Lock Set
Init. low
Signal on port pin
t
ACQ
Complete
PLL Configured and switched on
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