Clock Generator Module (CGM)

Technical Data MC68HC908AZ60A — Rev 2.0

190 Clock Generator Module (CGM) MOTOROLA

10.8.2 Stop Mode

The STOP instruction disables the CGM and holds low all CGM outputs

(CGMXCLK, CGMOUT, and CGMINT).

If CGMOUT is being driven by CGMVCLK and a STOP instruction is

executed; the PLL will clear the BCS bit in the PLL control register,

causing CGMOUT to be driven by CGMXCLK. When the MCU recovers

from STOP, the crystal clock divided by two drives CGMOUT and BCS

remains clear.

10.9 CGM During Break Interrupts

The BCFE bit in the break flag control register (BFCR) enables software

to clear status bits during the break state. See Break Module (BRK) on

page 203.

To allow software to clear status bits during a break interrupt, write a

logic 1 to the BCFE bit. If a status bit is cleared during the break state, it

remains cleared when the MCU exits the break state.

To protect the PLLF bit during the break state, write a logic 0 to the BCFE

bit. With BCFE at logic 0 (its default state), software can read and write

the PLL control register during the break state without affecting the PLLF

bit.

10.10 Acquisition/Lock Time Specifications

The acquisition and lock times of the PLL are, in many applications, the

most critical PLL design parameters. Proper design and use of the PLL

ensures the highest stability and lowest acquisition/lock times.

10.10.1 Acquisition/Lock Time Definitions

Typical control systems refer to the acquisition time or lock time as the

reaction time, within specified tolerances, of the system to a step input.

In a PLL, the step input occurs when the PLL is turned on or when it

suffers a noise hit. The tolerance is usually specified as a percent of the

Clock Generator Module (CGM)

Acquisition/Lock Time Specifications

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA Clock Generator Module (CGM) 191

step input or when the output settles to the desired value plus or minus

a percent of the frequency change. Therefore, the reaction time is

constant in this definition, regardless of the size of the step input. For

example, consider a system with a 5% acquisition time tolerance. If a

command instructs the system to change from 0 Hz to 1 MHz, the

acquisition time is the time taken for the frequency to reach

1MHz±50 kHz. Fifty kHz = 5% of the 1-MHz step input. If the system is

operating at 1 MHz and suffers a –100 kHz noise hit, the acquisition time

is the time taken to return from 900 kHz to 1 MHz ±5 kHz. Five kHz = 5%

of the 100-kHz step input.

Other systems refer to acquisition and lock times as the time the system

takes to reduce the error between the actual output and the desired

output to within specified tolerances. Therefore, the acquisition or lock

time varies according to the original error in the output. Minor errors may

not even be registered. Typical PLL applications prefer to use this

definition because the system requires the output frequency to be within

a certain tolerance of the desired frequency regardless of the size of the

initial error.

The discrepancy in these definitions makes it difficult to specify an

acquisition or lock time for a typical PLL. Therefore, the definitions for

acquisition and lock times for this module are:

• Acquisition time, t

acq

, is the time the PLL takes to reduce the error

between the actual output frequency and the desired output

frequency to less than the tracking mode entry tolerance, ∆

trk

Acquisition time is based on an initial frequency error,

des

–f

orig

)/f

des

, of not more than ±100%. In automatic bandwidth

control mode (see Manual and Automatic PLL Bandwidth

Modes on page 175), acquisition time expires when the ACQ bit

becomes set in the PLL bandwidth control register (PBWC).

• Lock time, t

Lock

, is the time the PLL takes to reduce the error

between the actual output frequency and the desired output

frequency to less than the lock mode entry tolerance, ∆

Lock

. Lock

time is based on an initial frequency error, (f

des

– f

orig

)/f

des

, of not

more than ±100%. In automatic bandwidth control mode, lock time

Clock Generator Module (CGM)

Technical Data MC68HC908AZ60A — Rev 2.0

192 Clock Generator Module (CGM) MOTOROLA

expires when the LOCK bit becomes set in the PLL bandwidth

control register (PBWC). (See Manual and Automatic PLL

Bandwidth Modes on page 175).

Obviously, the acquisition and lock times can vary according to how

large the frequency error is and may be shorter or longer in many cases.

10.10.2 Parametric Influences on Reaction Time

Acquisition and lock times are designed to be as short as possible while

still providing the highest possible stability. These reaction times are not

constant, however. Many factors directly and indirectly affect the

acquisition time.

The most critical parameter which affects the reaction times of the PLL

is the reference frequency, f

CGMRDV

(please reference Figure 10-1).

This frequency is the input to the phase detector and controls how often

the PLL makes corrections. For stability, the corrections must be small

compared to the desired frequency, so several corrections are required

to reduce the frequency error. Therefore, the slower the reference the

longer it takes to make these corrections. This parameter is also under

user control via the choice of crystal frequency f

CGMXCLK

Another critical parameter is the external filter capacitor. The PLL

modifies the voltage on the VCO by adding or subtracting charge from

this capacitor. Therefore, the rate at which the voltage changes for a

given frequency error (thus a change in charge) is proportional to the

capacitor size. The size of the capacitor also is related to the stability of

the PLL. If the capacitor is too small, the PLL cannot make small enough

adjustments to the voltage and the system cannot lock. If the capacitor

is too large, the PLL may not be able to adjust the voltage in a

reasonable time. See Choosing a Filter Capacitor on page 193.

Also important is the operating voltage potential applied to V

DDA

. The

power supply potential alters the characteristics of the PLL. A fixed value

is best. Variable supplies, such as batteries, are acceptable if they vary

within a known range at very slow speeds. Noise on the power supply is

not acceptable, because it causes small frequency errors which

continually change the acquisition time of the PLL.

Part #	8A/S6
Description	Incandescent S Light Lamp
Category	LAMP
Availability	In Stock
Qty	2

8A/S6

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