ON Semiconductor MC33074P

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Item Description: Operational Amplifiers - Op Amps 3-44V Quad 5mV VIO

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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

MC34071,2,4,A MC33071,2,4,A
http://onsemi.com
10
Figure 34. Supply Current versus
Supply Voltage
Figure 35. Power Supply Rejection
versus Temperature
Figure 36. Channel Separation versus Frequency Figure 37. Input Noise versus Frequency
V
CC
, |V
EE
|, SUPPLY VOLTAGE (V)
CC
I , SUPPLY CURRENT (mA)
0 5.0 10 15 20 25
T
A
= 25°C
T
A
= 125°C
T
A
= −55°C
T
A
, AMBIENT TEMPERATURE (°C)
PSR, POWER SUPPLY REJECTION (dB)
−55 −25 0 25 50 75 100 125
V
CC
= +15 V
V
EE
= −15 V
(V
CC
= +1.5 V)
(V
EE
= +1.5 V)
+PSR
−PSR
f, FREQUENCY (kHz)
CHANNEL SEPARATION (dB)
10 20 30 50 70 100 200 300
V
CC
= +15 V
V
EE
= −15 V
T
A
= 25°C
f, FREQUENCY (kHz)
n
e, INPUT NOICE VOLTAGE (
i, INPUT NOISE CURRENT (pA )
10 100 1.0 k 10 k 100 k
nV
Hz)
Hz
n
Voltage
Current
9.0
8.0
7.0
6.0
5.0
4.0
105
95
85
75
65
120
100
80
60
40
20
0
70
60
50
40
30
20
10
0
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0
V
O
A
DM
+
V
CC
V
EE
V
O
/A
DM
V
CC
+PSR = 20 Log
V
O
/A
DM
V
EE
−PSR = 20 Log
V
CC
= +15 V
V
EE
= −15 V
V
CM
= 0
T
A
= 25°C
APPLICATIONS INFORMATION
CIRCUIT DESCRIPTION/PERFORMANCE FEATURES
Although the bandwidth, slew rate, and settling time of the
MC34071 amplifier series are similar to op amp products
utilizing JFET input devices, these amplifiers offer other
additional distinct advantages as a result of the PNP
transistor differential input stage and an all NPN transistor
output stage.
Since the input common mode voltage range of this input
stage includes the V
EE
potential, single supply operation is
feasible to as low as 3.0 V with the common mode input
voltage at ground potential.
The input stage also allows differential input voltages up
to ±44 V, provided the maximum input voltage range is not
exceeded. Specifically, the input voltages must range
between V
EE
and V
CC
supply voltages as shown by the
maximum rating table. In practice, although not
recommended, the input voltages can exceed the V
CC
voltage by approximately 3.0 V and decrease below the V
EE
voltage by 0.3 V without causing product damage, although
output phase reversal may occur. It is also possible to source
up to approximately 5.0 mA of current from V
EE
through
either inputs clamping diode without damage or latching,
although phase reversal may again occur.
If one or both inputs exceed the upper common mode
voltage limit, the amplifier output is readily predictable and
may be in a low or high state depending on the existing input
bias conditions.
Since the input capacitance associated with the small
geometry input device is substantially lower (2.5 pF) than
the typical JFET input gate capacitance (5.0 pF), better
frequency response for a given input source resistance can
be achieved using the MC34071 series of amplifiers. This
performance feature becomes evident, for example, in fast
settling D−to−A current to voltage conversion applications
where the feedback resistance can form an input pole with
the input capacitance of the op amp. This input pole creates
a 2nd order system with the single pole op amp and is
therefore detrimental to its settling time. In this context,
lower input capacitance is desirable especially for higher
MC34071,2,4,A MC33071,2,4,A
http://onsemi.com
11
values of feedback resistances (lower current DACs). This
input pole can be compensated for by creating a feedback
zero with a capacitance across the feedback resistance, if
necessary, to reduce overshoot. For 2.0 k of feedback
resistance, the MC34071 series can settle to within 1/2 LSB
of 8−bits in 1.0 s, and within 1/2 LSB of 12−bits in 2.2 s
for a 10 V step. In a inverting unity gain fast settling
configuration, the symmetrical slew rate is ±13 V/s. In the
classic noninverting unity gain configuration, the output
positive slew rate is +10 V/s, and the corresponding
negative slew rate will exceed the positive slew rate as a
function of the fall time of the input waveform.
Since the bipolar input device matching characteristics
are superior to that of JFETs, a low untrimmed maximum
offset voltage of 3.0 mV prime and 5.0 mV downgrade can
be economically offered with high frequency performance
characteristics. This combination is ideal for low cost
precision, high speed quad op amp applications.
The all NPN output stage, shown in its basic form on the
equivalent circuit schematic, offers unique advantages over
the more conventional NPN/PNP transistor Class AB output
stage. A 10 k load resistance can swing within 1.0 V of the
positive rail (V
CC
), and within 0.3 V of the negative rail
(V
EE
), providing a 28.7 V
pp
swing from ±15 V supplies.
This large output swing becomes most noticeable at lower
supply voltages.
The positive swing is limited by the saturation voltage of
the current source transistor Q
7
, and V
BE
of the NPN pull up
transistor Q
17
, and the voltage drop associated with the short
circuit resistance, R
7
. The negative swing is limited by the
saturation voltage of the pull−down transistor Q
16
, the
voltage drop I
L
R
6
, and the voltage drop associated with
resistance R
7
, where I
L
is the sink load current. For small
valued sink currents, the above voltage drops are negligible,
allowing the negative swing voltage to approach within
millivolts of V
EE
. For large valued sink currents (>5.0 mA),
diode D3 clamps the voltage across R
6
, thus limiting the
negative swing to the saturation voltage of Q
16
, plus the
forward diode drop of D3 (V
EE
+1.0 V). Thus for a given
supply voltage, unprecedented peak−to−peak output voltage
swing is possible as indicated by the output swing
specifications.
If the load resistance is referenced to V
CC
instead of
ground for single supply applications, the maximum
possible output swing can be achieved for a given supply
voltage. For light load currents, the load resistance will pull
the output to V
CC
during the positive swing and the output
will pull the load resistance near ground during the negative
swing. The load resistance value should be much less than
that of the feedback resistance to maximize pull up
capability.
Because the PNP output emitter−follower transistor has
been eliminated, the MC34071 series offers a 20 mA
minimum current sink capability, typically to an output
voltage of (V
EE
+1.8 V). In single supply applications the
output can directly source or sink base current from a
common emitter NPN transistor for fast high current
switching applications.
In addition, the all NPN transistor output stage is
inherently fast, contributing to the bipolar amplifiers high
gain bandwidth product and fast settling capability. The
associated high frequency low output impedance (30 typ
@ 1.0 MHz) allows capacitive drive capability from 0 pF to
10,000 pF without oscillation in the unity closed loop gain
configuration. The 60° phase margin and 12 dB gain margin
as well as the general gain and phase characteristics are
virtually independent of the source/sink output swing
conditions. This allows easier system phase compensation,
since output swing will not be a phase consideration. The
high frequency characteristics of the MC34071 series also
allow excellent high frequency active filter capability,
especially for low voltage single supply applications.
Although the single supply specifications is defined at
5.0 V, these amplifiers are functional to 3.0 V @ 25°C
although slight changes in parametrics such as bandwidth,
slew rate, and DC gain may occur.
If power to this integrated circuit is applied in reverse
polarity or if the IC is installed backwards in a socket, large
unlimited current surges will occur through the device that
may result in device destruction.
Special static precautions are not necessary for these
bipolar amplifiers since there are no MOS transistors on the
die.
As with most high frequency amplifiers, proper lead
dress, component placement, and PC board layout should be
exercised for optimum frequency performance. For
example, long unshielded input or output leads may result in
unwanted input−output coupling. In order to preserve the
relatively low input capacitance associated with these
amplifiers, resistors connected to the inputs should be
immediately adjacent to the input pin to minimize additional
stray input capacitance. This not only minimizes the input
pole for optimum frequency response, but also minimizes
extraneous “pick up” at this node. Supply decoupling with
adequate capacitance immediately adjacent to the supply pin
is also important, particularly over temperature, since many
types of decoupling capacitors exhibit great impedance
changes over temperature.
The output of any one amplifier is current limited and thus
protected from a direct short to ground. However, under
such conditions, it is important not to allow the device to
exceed the maximum junction temperature rating. Typically
for ±15 V supplies, any one output can be shorted
continuously to ground without exceeding the maximum
temperature rating.
MC34071,2,4,A MC33071,2,4,A
http://onsemi.com
12
Figure 38. AC Coupled Noninverting Amplifier Figure 39. AC Coupled Inverting Amplifier
(Typical Single Supply Applications V
CC
= 5.0 V)
Figure 40. DC Coupled Inverting Amplifier
Maximum Output Swing
Figure 41. Unity Gain Buffer TTL Driver
Figure 42. Active High−Q Notch Filter
Figure 43. Active Bandpass Filter
+
V
CC
5.1 M
20 k
C
in
V
in
1.0 M
MC34071
V
O
0
3.7 V
pp
R
L
10 k
A
V
= 101
100 k
1.0 k
BW (−3.0 dB) = 45 kHz
C
O
V
O
36.6 mV
pp
+
3.7 V
pp
0
V
CC
V
O
100 k
C
in
10 k
100 k
C
O
R
L
10 k
68 k
V
in
370 mV
pp
A
V
= 10 BW (−3.0 dB) = 450 kHz
+
4.75 V
pp
V
O
V
O
V
CC
R
L
100 k
91 k
5.1 k
1.0 M
A
V
= 10
V
in
2.63 V
5.1 k
BW (−3.0 dB) = 450 kHz
+
V
in
2.5 V
0 0 to 10,000 pF
Cable
TTL Gate
+
V
in
V
O
16 k
C
0.01
32 k
2.0 R
2.0 C
0.02
f
o
= 1.0 kHz
f
o
=
V
in
0.2 Vdc
1
4RC
2.0 C
0.02
16 k
RR
+
V
in
V
O
V
CC
R3
2.2 k
C
0.047
R2
5.6 k
0.4 V
CC
R1
f
o
= 30 kHz
H
o
= 10
H
o
= 1.0
1.1 k
Given f
o
= Center Frequency
A
O
= Gain at Center Frequency
Choose Value f
o
, Q, A
o
, C
R3 =  R1 =  R2 =
Q R3 R1 R3
2H
o
4Q
2
R1−R3f
o
C
For less than 10% error from operational amplifier
Q
o
f
o
GBW
< 0.1
where f
o
and GBW are expressed in Hz.
C
0.047
MC34071
MC34071
MC34071
MC34071
MC34071
MC54/74XX
Then:
GBW = 4.5 MHz Typ.
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